1 ;;; verilog-mode.el --- major mode for editing verilog source in Emacs
3 ;; Copyright (C) 1996-2015 Free Software Foundation, Inc.
5 ;; Author: Michael McNamara <mac@verilog.com>
6 ;; Wilson Snyder <wsnyder@wsnyder.org>
7 ;; http://www.verilog.com
8 ;; http://www.veripool.org
10 ;; Keywords: languages
12 ;; Yoni Rabkin <yoni@rabkins.net> contacted the maintainer of this
13 ;; file on 19/3/2008, and the maintainer agreed that when a bug is
14 ;; filed in the Emacs bug reporting system against this file, a copy
15 ;; of the bug report be sent to the maintainer's email address.
17 ;; This code supports Emacs 21.1 and later
18 ;; And XEmacs 21.1 and later
19 ;; Please do not make changes that break Emacs 21. Thanks!
23 ;; This file is part of GNU Emacs.
25 ;; GNU Emacs is free software: you can redistribute it and/or modify
26 ;; it under the terms of the GNU General Public License as published by
27 ;; the Free Software Foundation, either version 3 of the License, or
28 ;; (at your option) any later version.
30 ;; GNU Emacs is distributed in the hope that it will be useful,
31 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
32 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 ;; GNU General Public License for more details.
35 ;; You should have received a copy of the GNU General Public License
36 ;; along with GNU Emacs. If not, see <http://www.gnu.org/licenses/>.
43 ;; A major mode for editing Verilog and SystemVerilog HDL source code (IEEE
44 ;; 1364-2005 and IEEE 1800-2012 standards). When you have entered Verilog
45 ;; mode, you may get more info by pressing C-h m. You may also get online
46 ;; help describing various functions by: C-h f <Name of function you want
49 ;; KNOWN BUGS / BUG REPORTS
50 ;; =======================
52 ;; SystemVerilog is a rapidly evolving language, and hence this mode is
53 ;; under continuous development. Please report any issues to the issue
56 ;; http://www.veripool.org/verilog-mode
58 ;; Please use verilog-submit-bug-report to submit a report; type C-c
59 ;; C-b to invoke this and as a result we will have a much easier time
60 ;; of reproducing the bug you find, and hence fixing it.
62 ;; INSTALLING THE MODE
63 ;; ===================
65 ;; An older version of this mode may be already installed as a part of
66 ;; your environment, and one method of updating would be to update
67 ;; your Emacs environment. Sometimes this is difficult for local
68 ;; political/control reasons, and hence you can always install a
69 ;; private copy (or even a shared copy) which overrides the system
72 ;; You can get step by step help in installing this file by going to
73 ;; <http://www.verilog.com/emacs_install.html>
75 ;; The short list of installation instructions are: To set up
76 ;; automatic Verilog mode, put this file in your load path, and put
77 ;; the following in code (please un comment it first!) in your
78 ;; .emacs, or in your site's site-load.el
80 ;; (autoload 'verilog-mode "verilog-mode" "Verilog mode" t )
81 ;; (add-to-list 'auto-mode-alist '("\\.[ds]?vh?\\'" . verilog-mode))
83 ;; Be sure to examine at the help for verilog-auto, and the other
84 ;; verilog-auto-* functions for some major coding time savers.
86 ;; If you want to customize Verilog mode to fit your needs better,
87 ;; you may add the below lines (the values of the variables presented
88 ;; here are the defaults). Note also that if you use an Emacs that
89 ;; supports custom, it's probably better to use the custom menu to
90 ;; edit these. If working as a member of a large team these settings
91 ;; should be common across all users (in a site-start file), or set
92 ;; in Local Variables in every file. Otherwise, different people's
93 ;; AUTO expansion may result different whitespace changes.
95 ;; ;; Enable syntax highlighting of **all** languages
96 ;; (global-font-lock-mode t)
98 ;; ;; User customization for Verilog mode
99 ;; (setq verilog-indent-level 3
100 ;; verilog-indent-level-module 3
101 ;; verilog-indent-level-declaration 3
102 ;; verilog-indent-level-behavioral 3
103 ;; verilog-indent-level-directive 1
104 ;; verilog-case-indent 2
105 ;; verilog-auto-newline t
106 ;; verilog-auto-indent-on-newline t
107 ;; verilog-tab-always-indent t
108 ;; verilog-auto-endcomments t
109 ;; verilog-minimum-comment-distance 40
110 ;; verilog-indent-begin-after-if t
111 ;; verilog-auto-lineup 'declarations
112 ;; verilog-highlight-p1800-keywords nil
113 ;; verilog-linter "my_lint_shell_command"
119 ;; See commit history at http://www.veripool.org/verilog-mode.html
120 ;; (This section is required to appease checkdoc.)
125 ;; This variable will always hold the version number of the mode
126 (defconst verilog-mode-version "2015-11-21-8112ca0-vpo-GNU"
127 "Version of this Verilog mode.")
128 (defconst verilog-mode-release-emacs t
129 "If non-nil, this version of Verilog mode was released with Emacs itself.")
131 (defun verilog-version ()
132 "Inform caller of the version of this file."
134 (message "Using verilog-mode version %s" verilog-mode-version))
136 ;; Insure we have certain packages, and deal with it if we don't
137 ;; Be sure to note which Emacs flavor and version added each feature.
139 ;; Provide stuff if we are XEmacs
140 (when (featurep 'xemacs)
145 (require 'regexp-opt)
147 ;; Bug in 19.28 through 19.30 skeleton.el, not provided.
154 (defmacro when (cond &rest body)
155 (list 'if cond (cons 'progn body))))
158 (if (fboundp 'unless)
160 (defmacro unless (cond &rest body)
161 (cons 'if (cons cond (cons nil body)))))
164 (if (fboundp 'store-match-data)
166 (defmacro store-match-data (&rest _args) nil))
169 (if (fboundp 'char-before)
171 (defmacro char-before (&rest _body)
172 (char-after (1- (point)))))
177 (defsubst point-at-bol (&optional N)
178 (save-excursion (beginning-of-line N) (point))))
183 (defsubst point-at-eol (&optional N)
184 (save-excursion (end-of-line N) (point))))
190 (if (fboundp 'match-string-no-properties)
192 (defsubst match-string-no-properties (num &optional string)
193 "Return string of text matched by last search, without text properties.
194 NUM specifies which parenthesized expression in the last regexp.
195 Value is nil if NUMth pair didn't match, or there were less than NUM pairs.
196 Zero means the entire text matched by the whole regexp or whole string.
197 STRING should be given if the last search was by `string-match' on STRING."
198 (if (match-beginning num)
202 (match-beginning num) (match-end num))))
203 (set-text-properties 0 (length result) nil result)
205 (buffer-substring-no-properties (match-beginning num)
210 (if (and (featurep 'custom) (fboundp 'custom-declare-variable))
211 nil ; We've got what we needed
212 ;; We have the old custom-library, hack around it!
213 (defmacro defgroup (&rest _args) nil)
214 (defmacro customize (&rest _args)
216 "Sorry, Customize is not available with this version of Emacs"))
217 (defmacro defcustom (var value doc &rest _args)
218 `(defvar ,var ,value ,doc))
220 (if (fboundp 'defface)
222 (defmacro defface (var values doc &rest _args)
226 (if (and (featurep 'custom) (fboundp 'customize-group))
227 nil ; We've got what we needed
228 ;; We have an intermediate custom-library, hack around it!
229 (defmacro customize-group (var &rest _args)
233 (defvar inhibit-modification-hooks)
234 (defvar inhibit-point-motion-hooks)
235 (defvar deactivate-mark)
238 ;; OK, do this stuff if we are NOT XEmacs:
239 (unless (featurep 'xemacs)
240 (unless (fboundp 'region-active-p)
241 (defmacro region-active-p ()
242 `(and transient-mark-mode mark-active))))
245 ;; Provide a regular expression optimization routine, using regexp-opt
246 ;; if provided by the user's elisp libraries
248 ;; The below were disabled when GNU Emacs 22 was released;
249 ;; perhaps some still need to be there to support Emacs 21.
250 (if (featurep 'xemacs)
251 (if (fboundp 'regexp-opt)
252 ;; regexp-opt is defined, does it take 3 or 2 arguments?
253 (if (fboundp 'function-max-args)
254 (let ((args (function-max-args `regexp-opt)))
256 ((eq args 3) ; It takes 3
257 (condition-case nil ; Hide this defun from emacses
258 ; with just a two input regexp
259 (defun verilog-regexp-opt (a b)
260 "Deal with differing number of required arguments for `regexp-opt'.
261 Call `regexp-opt' on A and B."
265 ((eq args 2) ; It takes 2
266 (defun verilog-regexp-opt (a b)
267 "Call `regexp-opt' on A and B."
271 ;; We can't tell; assume it takes 2
272 (defun verilog-regexp-opt (a b)
273 "Call `regexp-opt' on A and B."
276 ;; There is no regexp-opt, provide our own
277 (defun verilog-regexp-opt (strings &optional paren _shy)
278 (let ((open (if paren "\\(" "")) (close (if paren "\\)" "")))
279 (concat open (mapconcat 'regexp-quote strings "\\|") close)))
282 (defalias 'verilog-regexp-opt 'regexp-opt)))
284 ;; emacs >=22 has looking-back, but older emacs and xemacs don't.
285 ;; This function is lifted directly from emacs's subr.el
286 ;; so that it can be used by xemacs.
287 ;; The idea for this was borrowed from org-mode via this link:
288 ;; https://lists.gnu.org/archive/html/emacs-orgmode/2009-12/msg00032.html
291 ((fboundp 'looking-back)
292 (defalias 'verilog-looking-back 'looking-back))
294 (defun verilog-looking-back (regexp limit &optional greedy)
295 "Return non-nil if text before point matches regular expression REGEXP.
296 Like `looking-at' except matches before point, and is slower.
297 LIMIT if non-nil speeds up the search by specifying a minimum
298 starting position, to avoid checking matches that would start
301 If GREEDY is non-nil, extend the match backwards as far as
302 possible, stopping when a single additional previous character
303 cannot be part of a match for REGEXP. When the match is
304 extended, its starting position is allowed to occur before
307 As a general recommendation, try to avoid using `looking-back'
308 wherever possible, since it is slow."
309 (let ((start (point))
312 (and (re-search-backward (concat "\\(?:" regexp "\\)\\=") limit t)
316 (narrow-to-region (point-min) start)
317 (while (and (> pos (point-min))
321 (looking-at (concat "\\(?:" regexp "\\)\\'"))))
325 (looking-at (concat "\\(?:" regexp "\\)\\'")))))
326 (not (null pos)))))))
330 ((fboundp 'restore-buffer-modified-p)
331 ;; Faster, as does not update mode line when nothing changes
332 (defalias 'verilog-restore-buffer-modified-p 'restore-buffer-modified-p))
334 (defalias 'verilog-restore-buffer-modified-p 'set-buffer-modified-p))))
337 ;; Both xemacs and emacs
339 (require 'diff) ; diff-command and diff-switches
342 (require 'compile) ; compilation-error-regexp-alist-alist
345 (unless (fboundp 'buffer-chars-modified-tick) ; Emacs 22 added
346 (defmacro buffer-chars-modified-tick () (buffer-modified-tick)))
348 ;; Added in Emacs 24.1
350 (unless (fboundp 'prog-mode)
351 (define-derived-mode prog-mode fundamental-mode "Prog"))
355 (defun verilog-regexp-words (a)
356 "Call `regexp-opt' with word delimiters for the words A."
357 (concat "\\<" (verilog-regexp-opt a t) "\\>")))
358 (defun verilog-regexp-words (a)
359 "Call `regexp-opt' with word delimiters for the words A."
360 ;; The FAQ references this function, so user LISP sometimes calls it
361 (concat "\\<" (verilog-regexp-opt a t) "\\>"))
363 (defun verilog-easy-menu-filter (menu)
364 "Filter `easy-menu-define' MENU to support new features."
365 (cond ((not (featurep 'xemacs))
366 menu) ; GNU Emacs - passthru
367 ;; XEmacs doesn't support :help. Strip it.
368 ;; Recursively filter the a submenu
370 (mapcar 'verilog-easy-menu-filter menu))
371 ;; Look for [:help "blah"] and remove
373 (let ((i 0) (out []))
374 (while (< i (length menu))
375 (if (equal `:help (aref menu i))
377 (setq out (vconcat out (vector (aref menu i)))
380 (t menu))) ; Default - ok
381 ;;(verilog-easy-menu-filter
382 ;; `("Verilog" ("MA" ["SAA" nil :help "Help SAA"] ["SAB" nil :help "Help SAA"])
383 ;; "----" ["MB" nil :help "Help MB"]))
385 (defun verilog-define-abbrev (table name expansion &optional hook)
386 "Filter `define-abbrev' TABLE NAME EXPANSION and call HOOK.
387 Provides SYSTEM-FLAG in newer Emacs."
389 (define-abbrev table name expansion hook 0 t)
391 (define-abbrev table name expansion hook))))
393 (defun verilog-customize ()
394 "Customize variables and other settings used by Verilog-Mode."
396 (customize-group 'verilog-mode))
398 (defun verilog-font-customize ()
399 "Customize fonts used by Verilog-Mode."
401 (if (fboundp 'customize-apropos)
402 (customize-apropos "font-lock-*" 'faces)))
404 (defun verilog-booleanp (value)
405 "Return t if VALUE is boolean.
406 This implements GNU Emacs 22.1's `booleanp' function in earlier Emacs.
407 This function may be removed when Emacs 21 is no longer supported."
408 (or (equal value t) (equal value nil)))
410 (defun verilog-insert-last-command-event ()
411 "Insert the `last-command-event'."
412 (insert (if (featurep 'xemacs)
413 ;; XEmacs 21.5 doesn't like last-command-event
415 ;; And GNU Emacs 22 has obsoleted last-command-char
416 last-command-event)))
418 (defvar verilog-no-change-functions nil
419 "True if `after-change-functions' is disabled.
420 Use of `syntax-ppss' may break, as ppss's cache may get corrupted.")
422 (defvar verilog-in-hooks nil
423 "True when within a `verilog-run-hooks' block.")
425 (defmacro verilog-run-hooks (&rest hooks)
426 "Run each hook in HOOKS using `run-hooks'.
427 Set `verilog-in-hooks' during this time, to assist AUTO caches."
428 `(let ((verilog-in-hooks t))
429 (run-hooks ,@hooks)))
431 (defun verilog-syntax-ppss (&optional pos)
432 (when verilog-no-change-functions
434 (verilog-scan-cache-flush)
435 ;; else don't let the AUTO code itself get away with flushing the cache,
436 ;; as that'll make things very slow
438 (error "%s: Internal problem; use of syntax-ppss when cache may be corrupt"
439 (verilog-point-text))))
440 (if (fboundp 'syntax-ppss)
442 (parse-partial-sexp (point-min) (or pos (point)))))
444 (defgroup verilog-mode nil
445 "Major mode for Verilog source code."
449 ;; (defgroup verilog-mode-fonts nil
450 ;; "Facilitates easy customization fonts used in Verilog source text"
451 ;; :link '(customize-apropos "font-lock-*" 'faces)
452 ;; :group 'verilog-mode)
454 (defgroup verilog-mode-indent nil
455 "Customize indentation and highlighting of Verilog source text."
456 :group 'verilog-mode)
458 (defgroup verilog-mode-actions nil
459 "Customize actions on Verilog source text."
460 :group 'verilog-mode)
462 (defgroup verilog-mode-auto nil
463 "Customize AUTO actions when expanding Verilog source text."
464 :group 'verilog-mode)
466 (defvar verilog-debug nil
467 "Non-nil means enable debug messages for `verilog-mode' internals.")
469 (defvar verilog-warn-fatal nil
470 "Non-nil means `verilog-warn-error' warnings are fatal `error's.")
472 (defcustom verilog-linter
473 "echo 'No verilog-linter set, see \"M-x describe-variable verilog-linter\"'"
474 "Unix program and arguments to call to run a lint checker on Verilog source.
475 Depending on the `verilog-set-compile-command', this may be invoked when
476 you type \\[compile]. When the compile completes, \\[next-error] will take
477 you to the next lint error."
479 :group 'verilog-mode-actions)
480 ;; We don't mark it safe, as it's used as a shell command
482 (defcustom verilog-coverage
483 "echo 'No verilog-coverage set, see \"M-x describe-variable verilog-coverage\"'"
484 "Program and arguments to use to annotate for coverage Verilog source.
485 Depending on the `verilog-set-compile-command', this may be invoked when
486 you type \\[compile]. When the compile completes, \\[next-error] will take
487 you to the next lint error."
489 :group 'verilog-mode-actions)
490 ;; We don't mark it safe, as it's used as a shell command
492 (defcustom verilog-simulator
493 "echo 'No verilog-simulator set, see \"M-x describe-variable verilog-simulator\"'"
494 "Program and arguments to use to interpret Verilog source.
495 Depending on the `verilog-set-compile-command', this may be invoked when
496 you type \\[compile]. When the compile completes, \\[next-error] will take
497 you to the next lint error."
499 :group 'verilog-mode-actions)
500 ;; We don't mark it safe, as it's used as a shell command
502 (defcustom verilog-compiler
503 "echo 'No verilog-compiler set, see \"M-x describe-variable verilog-compiler\"'"
504 "Program and arguments to use to compile Verilog source.
505 Depending on the `verilog-set-compile-command', this may be invoked when
506 you type \\[compile]. When the compile completes, \\[next-error] will take
507 you to the next lint error."
509 :group 'verilog-mode-actions)
510 ;; We don't mark it safe, as it's used as a shell command
512 (defcustom verilog-preprocessor
513 ;; Very few tools give preprocessed output, so we'll default to Verilog-Perl
514 "vppreproc __FLAGS__ __FILE__"
515 "Program and arguments to use to preprocess Verilog source.
516 This is invoked with `verilog-preprocess', and depending on the
517 `verilog-set-compile-command', may also be invoked when you type
518 \\[compile]. When the compile completes, \\[next-error] will
519 take you to the next lint error."
521 :group 'verilog-mode-actions)
522 ;; We don't mark it safe, as it's used as a shell command
524 (defvar verilog-preprocess-history nil
525 "History for `verilog-preprocess'.")
527 (defvar verilog-tool 'verilog-linter
528 "Which tool to use for building compiler-command.
529 Either nil, `verilog-linter', `verilog-compiler',
530 `verilog-coverage', `verilog-preprocessor', or `verilog-simulator'.
531 Alternatively use the \"Choose Compilation Action\" menu. See
532 `verilog-set-compile-command' for more information.")
534 (defcustom verilog-highlight-translate-off nil
535 "Non-nil means background-highlight code excluded from translation.
536 That is, all code between \"// synopsys translate_off\" and
537 \"// synopsys translate_on\" is highlighted using a different background color
538 \(face `verilog-font-lock-translate-off-face').
540 Note: This will slow down on-the-fly fontification (and thus editing).
542 Note: Activate the new setting in a Verilog buffer by re-fontifying it (menu
543 entry \"Fontify Buffer\"). XEmacs: turn off and on font locking."
545 :group 'verilog-mode-indent)
546 ;; Note we don't use :safe, as that would break on Emacsen before 22.0.
547 (put 'verilog-highlight-translate-off 'safe-local-variable 'verilog-booleanp)
549 (defcustom verilog-auto-lineup 'declarations
550 "Type of statements to lineup across multiple lines.
551 If `all' is selected, then all line ups described below are done.
553 If `declarations', then just declarations are lined up with any
554 preceding declarations, taking into account widths and the like,
555 so or example the code:
562 If `assignment', then assignments are lined up with any preceding
563 assignments, so for example the code
564 a_long_variable <= b + c;
567 a_long_variable <= b + c;
570 In order to speed up editing, large blocks of statements are lined up
571 only when a \\[verilog-pretty-expr] is typed; and large blocks of declarations
572 are lineup only when \\[verilog-pretty-declarations] is typed."
574 :type '(radio (const :tag "Line up Assignments and Declarations" all)
575 (const :tag "Line up Assignment statements" assignments )
576 (const :tag "Line up Declarations" declarations)
577 (function :tag "Other"))
578 :group 'verilog-mode-indent )
579 (put 'verilog-auto-lineup 'safe-local-variable
580 '(lambda (x) (memq x '(nil all assignments declarations))))
582 (defcustom verilog-indent-level 3
583 "Indentation of Verilog statements with respect to containing block."
584 :group 'verilog-mode-indent
586 (put 'verilog-indent-level 'safe-local-variable 'integerp)
588 (defcustom verilog-indent-level-module 3
589 "Indentation of Module level Verilog statements (eg always, initial).
590 Set to 0 to get initial and always statements lined up on the left side of
592 :group 'verilog-mode-indent
594 (put 'verilog-indent-level-module 'safe-local-variable 'integerp)
596 (defcustom verilog-indent-level-declaration 3
597 "Indentation of declarations with respect to containing block.
598 Set to 0 to get them list right under containing block."
599 :group 'verilog-mode-indent
601 (put 'verilog-indent-level-declaration 'safe-local-variable 'integerp)
603 (defcustom verilog-indent-declaration-macros nil
604 "How to treat macro expansions in a declaration.
609 If non nil, treat as:
613 :group 'verilog-mode-indent
615 (put 'verilog-indent-declaration-macros 'safe-local-variable 'verilog-booleanp)
617 (defcustom verilog-indent-lists t
618 "How to treat indenting items in a list.
619 If t (the default), indent as:
620 always @( posedge a or
624 always @( posedge a or
626 :group 'verilog-mode-indent
628 (put 'verilog-indent-lists 'safe-local-variable 'verilog-booleanp)
630 (defcustom verilog-indent-level-behavioral 3
631 "Absolute indentation of first begin in a task or function block.
632 Set to 0 to get such code to start at the left side of the screen."
633 :group 'verilog-mode-indent
635 (put 'verilog-indent-level-behavioral 'safe-local-variable 'integerp)
637 (defcustom verilog-indent-level-directive 1
638 "Indentation to add to each level of \\=`ifdef declarations.
639 Set to 0 to have all directives start at the left side of the screen."
640 :group 'verilog-mode-indent
642 (put 'verilog-indent-level-directive 'safe-local-variable 'integerp)
644 (defcustom verilog-cexp-indent 2
645 "Indentation of Verilog statements split across lines."
646 :group 'verilog-mode-indent
648 (put 'verilog-cexp-indent 'safe-local-variable 'integerp)
650 (defcustom verilog-case-indent 2
651 "Indentation for case statements."
652 :group 'verilog-mode-indent
654 (put 'verilog-case-indent 'safe-local-variable 'integerp)
656 (defcustom verilog-auto-newline t
657 "Non-nil means automatically newline after semicolons."
658 :group 'verilog-mode-indent
660 (put 'verilog-auto-newline 'safe-local-variable 'verilog-booleanp)
662 (defcustom verilog-auto-indent-on-newline t
663 "Non-nil means automatically indent line after newline."
664 :group 'verilog-mode-indent
666 (put 'verilog-auto-indent-on-newline 'safe-local-variable 'verilog-booleanp)
668 (defcustom verilog-tab-always-indent t
669 "Non-nil means TAB should always re-indent the current line.
670 A nil value means TAB will only reindent when at the beginning of the line."
671 :group 'verilog-mode-indent
673 (put 'verilog-tab-always-indent 'safe-local-variable 'verilog-booleanp)
675 (defcustom verilog-tab-to-comment nil
676 "Non-nil means TAB moves to the right hand column in preparation for a comment."
677 :group 'verilog-mode-actions
679 (put 'verilog-tab-to-comment 'safe-local-variable 'verilog-booleanp)
681 (defcustom verilog-indent-begin-after-if t
682 "Non-nil means indent begin statements following if, else, while, etc.
683 Otherwise, line them up."
684 :group 'verilog-mode-indent
686 (put 'verilog-indent-begin-after-if 'safe-local-variable 'verilog-booleanp)
688 (defcustom verilog-align-ifelse nil
689 "Non-nil means align `else' under matching `if'.
690 Otherwise else is lined up with first character on line holding matching if."
691 :group 'verilog-mode-indent
693 (put 'verilog-align-ifelse 'safe-local-variable 'verilog-booleanp)
695 (defcustom verilog-minimum-comment-distance 10
696 "Minimum distance (in lines) between begin and end required before a comment.
697 Setting this variable to zero results in every end acquiring a comment; the
698 default avoids too many redundant comments in tight quarters."
699 :group 'verilog-mode-indent
701 (put 'verilog-minimum-comment-distance 'safe-local-variable 'integerp)
703 (defcustom verilog-highlight-p1800-keywords nil
704 "Non-nil means highlight words newly reserved by IEEE-1800.
705 These will appear in `verilog-font-lock-p1800-face' in order to gently
706 suggest changing where these words are used as variables to something else.
707 A nil value means highlight these words as appropriate for the SystemVerilog
708 IEEE-1800 standard. Note that changing this will require restarting Emacs
709 to see the effect as font color choices are cached by Emacs."
710 :group 'verilog-mode-indent
712 (put 'verilog-highlight-p1800-keywords 'safe-local-variable 'verilog-booleanp)
714 (defcustom verilog-highlight-grouping-keywords nil
715 "Non-nil means highlight grouping keywords more dramatically.
716 If false, these words are in the `font-lock-type-face'; if True
717 then they are in `verilog-font-lock-grouping-keywords-face'.
718 Some find that special highlighting on these grouping constructs
719 allow the structure of the code to be understood at a glance."
720 :group 'verilog-mode-indent
722 (put 'verilog-highlight-grouping-keywords 'safe-local-variable 'verilog-booleanp)
724 (defcustom verilog-highlight-modules nil
725 "Non-nil means highlight module statements for `verilog-load-file-at-point'.
726 When true, mousing over module names will allow jumping to the
727 module definition. If false, this is not supported. Setting
728 this is experimental, and may lead to bad performance."
729 :group 'verilog-mode-indent
731 (put 'verilog-highlight-modules 'safe-local-variable 'verilog-booleanp)
733 (defcustom verilog-highlight-includes t
734 "Non-nil means highlight module statements for `verilog-load-file-at-point'.
735 When true, mousing over include file names will allow jumping to the
736 file referenced. If false, this is not supported."
737 :group 'verilog-mode-indent
739 (put 'verilog-highlight-includes 'safe-local-variable 'verilog-booleanp)
741 (defcustom verilog-auto-declare-nettype nil
742 "Non-nil specifies the data type to use with `verilog-auto-input' etc.
743 Set this to \"wire\" if the Verilog code uses \"\\=`default_nettype
744 none\". Note using \\=`default_nettype none isn't recommended practice; this
745 mode is experimental."
746 :version "24.1" ; rev670
747 :group 'verilog-mode-actions
749 (put 'verilog-auto-declare-nettype 'safe-local-variable `stringp)
751 (defcustom verilog-auto-wire-type nil
752 "Non-nil specifies the data type to use with `verilog-auto-wire' etc.
753 Set this to \"logic\" for SystemVerilog code, or use `verilog-auto-logic'."
754 :version "24.1" ; rev673
755 :group 'verilog-mode-actions
757 (put 'verilog-auto-wire-type 'safe-local-variable `stringp)
759 (defcustom verilog-auto-endcomments t
760 "Non-nil means insert a comment /* ... */ after `end's.
761 The name of the function or case will be set between the braces."
762 :group 'verilog-mode-actions
764 (put 'verilog-auto-endcomments 'safe-local-variable 'verilog-booleanp)
766 (defcustom verilog-auto-delete-trailing-whitespace nil
767 "Non-nil means to `delete-trailing-whitespace' in `verilog-auto'."
768 :version "24.1" ; rev703
769 :group 'verilog-mode-actions
771 (put 'verilog-auto-delete-trailing-whitespace 'safe-local-variable 'verilog-booleanp)
773 (defcustom verilog-auto-ignore-concat nil
774 "Non-nil means ignore signals in {...} concatenations for AUTOWIRE etc.
775 This will exclude signals referenced as pin connections in {...}
776 from AUTOWIRE, AUTOOUTPUT and friends. This flag should be set
777 for backward compatibility only and not set in new designs; it
778 may be removed in future versions."
779 :group 'verilog-mode-actions
781 (put 'verilog-auto-ignore-concat 'safe-local-variable 'verilog-booleanp)
783 (defcustom verilog-auto-read-includes nil
784 "Non-nil means to automatically read includes before AUTOs.
785 This will do a `verilog-read-defines' and `verilog-read-includes' before
786 each AUTO expansion. This makes it easier to embed defines and includes,
787 but can result in very slow reading times if there are many or large
789 :group 'verilog-mode-actions
791 (put 'verilog-auto-read-includes 'safe-local-variable 'verilog-booleanp)
793 (defcustom verilog-auto-save-policy nil
794 "Non-nil indicates action to take when saving a Verilog buffer with AUTOs.
795 A value of `force' will always do a \\[verilog-auto] automatically if
796 needed on every save. A value of `detect' will do \\[verilog-auto]
797 automatically when it thinks necessary. A value of `ask' will query the
798 user when it thinks updating is needed.
800 You should not rely on the `ask' or `detect' policies, they are safeguards
801 only. They do not detect when AUTOINSTs need to be updated because a
802 sub-module's port list has changed."
803 :group 'verilog-mode-actions
804 :type '(choice (const nil) (const ask) (const detect) (const force)))
806 (defcustom verilog-auto-star-expand t
807 "Non-nil means to expand SystemVerilog .* instance ports.
808 They will be expanded in the same way as if there was an AUTOINST in the
809 instantiation. See also `verilog-auto-star' and `verilog-auto-star-save'."
810 :group 'verilog-mode-actions
812 (put 'verilog-auto-star-expand 'safe-local-variable 'verilog-booleanp)
814 (defcustom verilog-auto-star-save nil
815 "Non-nil means save to disk SystemVerilog .* instance expansions.
816 A nil value indicates direct connections will be removed before saving.
817 Only meaningful to those created due to `verilog-auto-star-expand' being set.
819 Instead of setting this, you may want to use /*AUTOINST*/, which will
821 :group 'verilog-mode-actions
823 (put 'verilog-auto-star-save 'safe-local-variable 'verilog-booleanp)
825 (defvar verilog-auto-update-tick nil
826 "Modification tick at which autos were last performed.")
828 (defvar verilog-auto-last-file-locals nil
829 "Text from file-local-variables during last evaluation.")
831 (defvar verilog-diff-function 'verilog-diff-report
832 "Function to run when `verilog-diff-auto' detects differences.
833 Function takes three arguments, the original buffer, the
834 difference buffer, and the point in original buffer with the
837 (defvar verilog-diff-ignore-regexp nil
838 "Non-nil specifies regexp which `verilog-diff-auto' will ignore.
839 This is typically nil.")
846 (defvar verilog-error-regexp-added nil)
848 (defvar verilog-error-regexp-emacs-alist
851 "\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 3)
853 "([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 1 3)
855 ".*\\*[WE],[0-9A-Z]+\\(\\[[0-9A-Z_,]+\\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)" 2 3)
857 "[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 2)
859 "\\(WARNING\\|ERROR\\|INFO\\)[^:]*: \\([^,]+\\),\\s-+\\(line \\)?\\([0-9]+\\):" 2 4 )
862 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
863 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 2 5)
865 "\\(Error\\|Warning\\).*in file (\\([^ \t]+\\) at line *\\([0-9]+\\))" 2 3)
867 "\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 3)
869 "Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 2)
871 "\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 3)
873 "syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 2)
875 "%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4)
877 "^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 1 2)
879 "List of regexps for Verilog compilers.
880 See `compilation-error-regexp-alist' for the formatting. For Emacs 22+.")
882 (defvar verilog-error-regexp-xemacs-alist
883 ;; Emacs form is '((v-tool "re" 1 2) ...)
884 ;; XEmacs form is '(verilog ("re" 1 2) ...)
885 ;; So we can just map from Emacs to XEmacs
886 (cons 'verilog (mapcar 'cdr verilog-error-regexp-emacs-alist))
887 "List of regexps for Verilog compilers.
888 See `compilation-error-regexp-alist-alist' for the formatting. For XEmacs.")
890 (defvar verilog-error-font-lock-keywords
893 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t)
894 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t)
896 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 1 bold t)
897 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 3 bold t)
898 ;; verilog-IES (nc-verilog)
899 (".*\\*[WE],[0-9A-Z]+\\(\\[[0-9A-Z_,]+\\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)|" 2 bold t)
900 (".*\\*[WE],[0-9A-Z]+\\(\\[[0-9A-Z_,]+\\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)|" 3 bold t)
901 ;; verilog-surefire-1
902 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 bold t)
903 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 2 bold t)
904 ;; verilog-surefire-2
905 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 2 bold t)
906 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 3 bold t)
909 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
910 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t)
912 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
913 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t)
915 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 bold t)
916 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 3 bold t)
918 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t)
919 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t)
921 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t)
922 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 3 bold t)
924 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 bold t)
925 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t)
927 (".*%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 bold t)
928 (".*%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 4 bold t)
930 ("^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 1 bold t)
931 ("^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 2 bold t)
933 "Keywords to also highlight in Verilog *compilation* buffers.
934 Only used in XEmacs; GNU Emacs uses `verilog-error-regexp-emacs-alist'.")
936 (defcustom verilog-library-flags '("")
937 "List of standard Verilog arguments to use for /*AUTOINST*/.
938 These arguments are used to find files for `verilog-auto', and match
939 the flags accepted by a standard Verilog-XL simulator.
941 -f filename Reads more `verilog-library-flags' from the filename.
942 +incdir+dir Adds the directory to `verilog-library-directories'.
943 -Idir Adds the directory to `verilog-library-directories'.
944 -y dir Adds the directory to `verilog-library-directories'.
945 +libext+.v Adds the extensions to `verilog-library-extensions'.
946 -v filename Adds the filename to `verilog-library-files'.
948 filename Adds the filename to `verilog-library-files'.
949 This is not recommended, -v is a better choice.
951 You might want these defined in each file; put at the *END* of your file
955 // verilog-library-flags:(\"-y dir -y otherdir\")
958 Verilog-mode attempts to detect changes to this local variable, but they
959 are only insured to be correct when the file is first visited. Thus if you
960 have problems, use \\[find-alternate-file] RET to have these take effect.
962 See also the variables mentioned above."
963 :group 'verilog-mode-auto
964 :type '(repeat string))
965 (put 'verilog-library-flags 'safe-local-variable 'listp)
967 (defcustom verilog-library-directories '(".")
968 "List of directories when looking for files for /*AUTOINST*/.
969 The directory may be relative to the current file, or absolute.
970 Environment variables are also expanded in the directory names.
971 Having at least the current directory is a good idea.
973 You might want these defined in each file; put at the *END* of your file
977 // verilog-library-directories:(\".\" \"subdir\" \"subdir2\")
980 Verilog-mode attempts to detect changes to this local variable, but they
981 are only insured to be correct when the file is first visited. Thus if you
982 have problems, use \\[find-alternate-file] RET to have these take effect.
984 See also `verilog-library-flags', `verilog-library-files'
985 and `verilog-library-extensions'."
986 :group 'verilog-mode-auto
987 :type '(repeat file))
988 (put 'verilog-library-directories 'safe-local-variable 'listp)
990 (defcustom verilog-library-files '()
991 "List of files to search for modules.
992 AUTOINST will use this when it needs to resolve a module name.
993 This is a complete path, usually to a technology file with many standard
996 You might want these defined in each file; put at the *END* of your file
1000 // verilog-library-files:(\"/some/path/technology.v\" \"/some/path/tech2.v\")
1003 Verilog-mode attempts to detect changes to this local variable, but they
1004 are only insured to be correct when the file is first visited. Thus if you
1005 have problems, use \\[find-alternate-file] RET to have these take effect.
1007 See also `verilog-library-flags', `verilog-library-directories'."
1008 :group 'verilog-mode-auto
1009 :type '(repeat directory))
1010 (put 'verilog-library-files 'safe-local-variable 'listp)
1012 (defcustom verilog-library-extensions '(".v" ".sv")
1013 "List of extensions to use when looking for files for /*AUTOINST*/.
1014 See also `verilog-library-flags', `verilog-library-directories'."
1015 :type '(repeat string)
1016 :group 'verilog-mode-auto)
1017 (put 'verilog-library-extensions 'safe-local-variable 'listp)
1019 (defcustom verilog-active-low-regexp nil
1020 "If true, treat signals matching this regexp as active low.
1021 This is used for AUTORESET and AUTOTIEOFF. For proper behavior,
1022 you will probably also need `verilog-auto-reset-widths' set."
1023 :group 'verilog-mode-auto
1024 :type '(choice (const nil) regexp))
1025 (put 'verilog-active-low-regexp 'safe-local-variable 'stringp)
1027 (defcustom verilog-auto-sense-include-inputs nil
1028 "Non-nil means AUTOSENSE should include all inputs.
1029 If nil, only inputs that are NOT output signals in the same block are
1031 :group 'verilog-mode-auto
1033 (put 'verilog-auto-sense-include-inputs 'safe-local-variable 'verilog-booleanp)
1035 (defcustom verilog-auto-sense-defines-constant nil
1036 "Non-nil means AUTOSENSE should assume all defines represent constants.
1037 When true, the defines will not be included in sensitivity lists. To
1038 maintain compatibility with other sites, this should be set at the bottom
1039 of each Verilog file that requires it, rather than being set globally."
1040 :group 'verilog-mode-auto
1042 (put 'verilog-auto-sense-defines-constant 'safe-local-variable 'verilog-booleanp)
1044 (defcustom verilog-auto-reset-blocking-in-non t
1045 "Non-nil means AUTORESET will reset blocking statements.
1046 When true, AUTORESET will reset in blocking statements those
1047 signals which were assigned with blocking assignments (=) even in
1048 a block with non-blocking assignments (<=).
1050 If nil, all blocking assigned signals are ignored when any
1051 non-blocking assignment is in the AUTORESET block. This allows
1052 blocking assignments to be used for temporary values and not have
1053 those temporaries reset. See example in `verilog-auto-reset'."
1054 :version "24.1" ; rev718
1056 :group 'verilog-mode-auto)
1057 (put 'verilog-auto-reset-blocking-in-non 'safe-local-variable 'verilog-booleanp)
1059 (defcustom verilog-auto-reset-widths t
1060 "True means AUTORESET should determine the width of signals.
1061 This is then used to set the width of the zero (32'h0 for example). This
1062 is required by some lint tools that aren't smart enough to ignore widths of
1063 the constant zero. This may result in ugly code when parameters determine
1064 the MSB or LSB of a signal inside an AUTORESET.
1066 If nil, AUTORESET uses \"0\" as the constant.
1068 If `unbased', AUTORESET used the unbased unsized literal \"\\='0\"
1069 as the constant. This setting is strongly recommended for
1070 SystemVerilog designs."
1072 :group 'verilog-mode-auto)
1073 (put 'verilog-auto-reset-widths 'safe-local-variable
1074 '(lambda (x) (memq x '(nil t unbased))))
1076 (defcustom verilog-assignment-delay ""
1077 "Text used for delays in delayed assignments. Add a trailing space if set."
1078 :group 'verilog-mode-auto
1080 (put 'verilog-assignment-delay 'safe-local-variable 'stringp)
1082 (defcustom verilog-auto-arg-format 'packed
1083 "Formatting to use for AUTOARG signal names.
1084 If `packed', then as many inputs and outputs that fit within
1085 `fill-column' will be put onto one line.
1087 If `single', then a single input or output will be put onto each
1090 :type '(radio (const :tag "Line up Assignments and Declarations" packed)
1091 (const :tag "Line up Assignment statements" single))
1092 :group 'verilog-mode-auto)
1093 (put 'verilog-auto-arg-format 'safe-local-variable
1094 '(lambda (x) (memq x '(packed single))))
1096 (defcustom verilog-auto-arg-sort nil
1097 "Non-nil means AUTOARG signal names will be sorted, not in declaration order.
1098 Declaration order is advantageous with order based instantiations
1099 and is the default for backward compatibility. Sorted order
1100 reduces changes when declarations are moved around in a file, and
1101 it's bad practice to rely on order based instantiations anyhow.
1103 See also `verilog-auto-inst-sort'."
1104 :group 'verilog-mode-auto
1106 (put 'verilog-auto-arg-sort 'safe-local-variable 'verilog-booleanp)
1108 (defcustom verilog-auto-inst-dot-name nil
1109 "Non-nil means when creating ports with AUTOINST, use .name syntax.
1110 This will use \".port\" instead of \".port(port)\" when possible.
1111 This is only legal in SystemVerilog files, and will confuse older
1112 simulators. Setting `verilog-auto-inst-vector' to nil may also
1113 be desirable to increase how often .name will be used."
1114 :group 'verilog-mode-auto
1116 (put 'verilog-auto-inst-dot-name 'safe-local-variable 'verilog-booleanp)
1118 (defcustom verilog-auto-inst-param-value nil
1119 "Non-nil means AUTOINST will replace parameters with the parameter value.
1120 If nil, leave parameters as symbolic names.
1122 Parameters must be in Verilog 2001 format #(...), and if a parameter is not
1123 listed as such there (as when the default value is acceptable), it will not
1124 be replaced, and will remain symbolic.
1126 For example, imagine a submodule uses parameters to declare the size of its
1127 inputs. This is then used by an upper module:
1129 module InstModule (o,i);
1131 input [WIDTH-1:0] i;
1141 Note even though PARAM=10, the AUTOINST has left the parameter as a
1142 symbolic name. If `verilog-auto-inst-param-value' is set, this will
1151 :group 'verilog-mode-auto
1153 (put 'verilog-auto-inst-param-value 'safe-local-variable 'verilog-booleanp)
1155 (defcustom verilog-auto-inst-sort nil
1156 "Non-nil means AUTOINST signals will be sorted, not in declaration order.
1157 Also affects AUTOINSTPARAM. Declaration order is the default for
1158 backward compatibility, and as some teams prefer signals that are
1159 declared together to remain together. Sorted order reduces
1160 changes when declarations are moved around in a file.
1162 See also `verilog-auto-arg-sort'."
1163 :version "24.1" ; rev688
1164 :group 'verilog-mode-auto
1166 (put 'verilog-auto-inst-sort 'safe-local-variable 'verilog-booleanp)
1168 (defcustom verilog-auto-inst-vector t
1169 "Non-nil means when creating default ports with AUTOINST, use bus subscripts.
1170 If nil, skip the subscript when it matches the entire bus as declared in
1171 the module (AUTOWIRE signals always are subscripted, you must manually
1172 declare the wire to have the subscripts removed.) Setting this to nil may
1173 speed up some simulators, but is less general and harder to read, so avoid."
1174 :group 'verilog-mode-auto
1176 (put 'verilog-auto-inst-vector 'safe-local-variable 'verilog-booleanp)
1178 (defcustom verilog-auto-inst-template-numbers nil
1179 "If true, when creating templated ports with AUTOINST, add a comment.
1181 If t, the comment will add the line number of the template that
1182 was used for that port declaration. This setting is suggested
1183 only for debugging use, as regular use may cause a large numbers
1186 If `lhs', the comment will show the left hand side of the
1187 AUTO_TEMPLATE rule that is matched. This is less precise than
1188 numbering (t) when multiple rules have the same pin name, but
1189 won't merge conflict."
1190 :group 'verilog-mode-auto
1191 :type '(choice (const nil) (const t) (const lhs)))
1192 (put 'verilog-auto-inst-template-numbers 'safe-local-variable
1193 '(lambda (x) (memq x '(nil t lhs))))
1195 (defcustom verilog-auto-inst-column 40
1196 "Indent-to column number for net name part of AUTOINST created pin."
1197 :group 'verilog-mode-indent
1199 (put 'verilog-auto-inst-column 'safe-local-variable 'integerp)
1201 (defcustom verilog-auto-inst-interfaced-ports nil
1202 "Non-nil means include interfaced ports in AUTOINST expansions."
1203 :version "24.3" ; rev773, default change rev815
1204 :group 'verilog-mode-auto
1206 (put 'verilog-auto-inst-interfaced-ports 'safe-local-variable 'verilog-booleanp)
1208 (defcustom verilog-auto-input-ignore-regexp nil
1209 "If non-nil, when creating AUTOINPUT, ignore signals matching this regexp.
1210 See the \\[verilog-faq] for examples on using this."
1211 :group 'verilog-mode-auto
1212 :type '(choice (const nil) regexp))
1213 (put 'verilog-auto-input-ignore-regexp 'safe-local-variable 'stringp)
1215 (defcustom verilog-auto-inout-ignore-regexp nil
1216 "If non-nil, when creating AUTOINOUT, ignore signals matching this regexp.
1217 See the \\[verilog-faq] for examples on using this."
1218 :group 'verilog-mode-auto
1219 :type '(choice (const nil) regexp))
1220 (put 'verilog-auto-inout-ignore-regexp 'safe-local-variable 'stringp)
1222 (defcustom verilog-auto-output-ignore-regexp nil
1223 "If non-nil, when creating AUTOOUTPUT, ignore signals matching this regexp.
1224 See the \\[verilog-faq] for examples on using this."
1225 :group 'verilog-mode-auto
1226 :type '(choice (const nil) regexp))
1227 (put 'verilog-auto-output-ignore-regexp 'safe-local-variable 'stringp)
1229 (defcustom verilog-auto-template-warn-unused nil
1230 "Non-nil means report warning if an AUTO_TEMPLATE line is not used.
1231 This feature is not supported before Emacs 21.1 or XEmacs 21.4."
1232 :version "24.3" ; rev787
1233 :group 'verilog-mode-auto
1235 (put 'verilog-auto-template-warn-unused 'safe-local-variable 'verilog-booleanp)
1237 (defcustom verilog-auto-tieoff-declaration "wire"
1238 "Data type used for the declaration for AUTOTIEOFF.
1239 If \"wire\" then create a wire, if \"assign\" create an
1240 assignment, else the data type for variable creation."
1241 :version "24.1" ; rev713
1242 :group 'verilog-mode-auto
1244 (put 'verilog-auto-tieoff-declaration 'safe-local-variable 'stringp)
1246 (defcustom verilog-auto-tieoff-ignore-regexp nil
1247 "If non-nil, when creating AUTOTIEOFF, ignore signals matching this regexp.
1248 See the \\[verilog-faq] for examples on using this."
1249 :group 'verilog-mode-auto
1250 :type '(choice (const nil) regexp))
1251 (put 'verilog-auto-tieoff-ignore-regexp 'safe-local-variable 'stringp)
1253 (defcustom verilog-auto-unused-ignore-regexp nil
1254 "If non-nil, when creating AUTOUNUSED, ignore signals matching this regexp.
1255 See the \\[verilog-faq] for examples on using this."
1256 :group 'verilog-mode-auto
1257 :type '(choice (const nil) regexp))
1258 (put 'verilog-auto-unused-ignore-regexp 'safe-local-variable 'stringp)
1260 (defcustom verilog-case-fold t
1261 "Non-nil means `verilog-mode' regexps should ignore case.
1262 This variable is t for backward compatibility; nil is suggested."
1264 :group 'verilog-mode
1266 (put 'verilog-case-fold 'safe-local-variable 'verilog-booleanp)
1268 (defcustom verilog-typedef-regexp nil
1269 "If non-nil, regular expression that matches Verilog-2001 typedef names.
1270 For example, \"_t$\" matches typedefs named with _t, as in the C language.
1271 See also `verilog-case-fold'."
1272 :group 'verilog-mode-auto
1273 :type '(choice (const nil) regexp))
1274 (put 'verilog-typedef-regexp 'safe-local-variable 'stringp)
1276 (defcustom verilog-mode-hook 'verilog-set-compile-command
1277 "Hook run after Verilog mode is loaded."
1279 :group 'verilog-mode)
1281 (defcustom verilog-auto-hook nil
1282 "Hook run after `verilog-mode' updates AUTOs."
1283 :group 'verilog-mode-auto
1286 (defcustom verilog-before-auto-hook nil
1287 "Hook run before `verilog-mode' updates AUTOs."
1288 :group 'verilog-mode-auto
1291 (defcustom verilog-delete-auto-hook nil
1292 "Hook run after `verilog-mode' deletes AUTOs."
1293 :group 'verilog-mode-auto
1296 (defcustom verilog-before-delete-auto-hook nil
1297 "Hook run before `verilog-mode' deletes AUTOs."
1298 :group 'verilog-mode-auto
1301 (defcustom verilog-getopt-flags-hook nil
1302 "Hook run after `verilog-getopt-flags' determines the Verilog option lists."
1303 :group 'verilog-mode-auto
1306 (defcustom verilog-before-getopt-flags-hook nil
1307 "Hook run before `verilog-getopt-flags' determines the Verilog option lists."
1308 :group 'verilog-mode-auto
1311 (defcustom verilog-before-save-font-hook nil
1312 "Hook run before `verilog-save-font-mods' removes highlighting."
1313 :version "24.3" ; rev735
1314 :group 'verilog-mode-auto
1317 (defcustom verilog-after-save-font-hook nil
1318 "Hook run after `verilog-save-font-mods' restores highlighting."
1319 :version "24.3" ; rev735
1320 :group 'verilog-mode-auto
1323 (defvar verilog-imenu-generic-expression
1324 '((nil "^\\s-*\\(\\(m\\(odule\\|acromodule\\)\\)\\|primitive\\)\\s-+\\([a-zA-Z0-9_.:]+\\)" 4)
1325 ("*Vars*" "^\\s-*\\(reg\\|wire\\)\\s-+\\(\\|\\[[^]]+\\]\\s-+\\)\\([A-Za-z0-9_]+\\)" 3))
1326 "Imenu expression for Verilog mode. See `imenu-generic-expression'.")
1329 ;; provide a verilog-header function.
1330 ;; Customization variables:
1332 (defvar verilog-date-scientific-format nil
1333 "If non-nil, dates are written in scientific format (e.g. 1997/09/17).
1334 If nil, in European format (e.g. 17.09.1997). The brain-dead American
1335 format (e.g. 09/17/1997) is not supported.")
1337 (defvar verilog-company nil
1338 "Default name of Company for Verilog header.
1339 If set will become buffer local.")
1340 (make-variable-buffer-local 'verilog-company)
1342 (defvar verilog-project nil
1343 "Default name of Project for Verilog header.
1344 If set will become buffer local.")
1345 (make-variable-buffer-local 'verilog-project)
1347 ;;; Keymap and Menu:
1350 (defvar verilog-mode-map
1351 (let ((map (make-sparse-keymap)))
1352 (define-key map ";" 'electric-verilog-semi)
1353 (define-key map [(control 59)] 'electric-verilog-semi-with-comment)
1354 (define-key map ":" 'electric-verilog-colon)
1355 ;;(define-key map "=" 'electric-verilog-equal)
1356 (define-key map "`" 'electric-verilog-tick)
1357 (define-key map "\t" 'electric-verilog-tab)
1358 (define-key map "\r" 'electric-verilog-terminate-line)
1359 ;; backspace/delete key bindings
1360 (define-key map [backspace] 'backward-delete-char-untabify)
1361 (unless (boundp 'delete-key-deletes-forward) ; XEmacs variable
1362 (define-key map [delete] 'delete-char)
1363 (define-key map [(meta delete)] 'kill-word))
1364 (define-key map "\M-\C-b" 'electric-verilog-backward-sexp)
1365 (define-key map "\M-\C-f" 'electric-verilog-forward-sexp)
1366 (define-key map "\M-\r" `electric-verilog-terminate-and-indent)
1367 (define-key map "\M-\t" 'verilog-complete-word)
1368 (define-key map "\M-?" 'verilog-show-completions)
1369 ;; Note \C-c and letter are reserved for users
1370 (define-key map "\C-c`" 'verilog-lint-off)
1371 (define-key map "\C-c*" 'verilog-delete-auto-star-implicit)
1372 (define-key map "\C-c?" 'verilog-diff-auto)
1373 (define-key map "\C-c\C-r" 'verilog-label-be)
1374 (define-key map "\C-c\C-i" 'verilog-pretty-declarations)
1375 (define-key map "\C-c=" 'verilog-pretty-expr)
1376 (define-key map "\C-c\C-b" 'verilog-submit-bug-report)
1377 (define-key map "\M-*" 'verilog-star-comment)
1378 (define-key map "\C-c\C-c" 'verilog-comment-region)
1379 (define-key map "\C-c\C-u" 'verilog-uncomment-region)
1380 (when (featurep 'xemacs)
1381 (define-key map [(meta control h)] 'verilog-mark-defun)
1382 (define-key map "\M-\C-a" 'verilog-beg-of-defun)
1383 (define-key map "\M-\C-e" 'verilog-end-of-defun))
1384 (define-key map "\C-c\C-d" 'verilog-goto-defun)
1385 (define-key map "\C-c\C-k" 'verilog-delete-auto)
1386 (define-key map "\C-c\C-a" 'verilog-auto)
1387 (define-key map "\C-c\C-s" 'verilog-auto-save-compile)
1388 (define-key map "\C-c\C-p" 'verilog-preprocess)
1389 (define-key map "\C-c\C-z" 'verilog-inject-auto)
1390 (define-key map "\C-c\C-e" 'verilog-expand-vector)
1391 (define-key map "\C-c\C-h" 'verilog-header)
1393 "Keymap used in Verilog mode.")
1397 verilog-menu verilog-mode-map "Menu for Verilog mode"
1398 (verilog-easy-menu-filter
1400 ("Choose Compilation Action"
1403 (setq verilog-tool nil)
1404 (verilog-set-compile-command))
1406 :selected (equal verilog-tool nil)
1407 :help "When invoking compilation, use compile-command"]
1410 (setq verilog-tool 'verilog-linter)
1411 (verilog-set-compile-command))
1413 :selected (equal verilog-tool `verilog-linter)
1414 :help "When invoking compilation, use lint checker"]
1417 (setq verilog-tool 'verilog-coverage)
1418 (verilog-set-compile-command))
1420 :selected (equal verilog-tool `verilog-coverage)
1421 :help "When invoking compilation, annotate for coverage"]
1424 (setq verilog-tool 'verilog-simulator)
1425 (verilog-set-compile-command))
1427 :selected (equal verilog-tool `verilog-simulator)
1428 :help "When invoking compilation, interpret Verilog source"]
1431 (setq verilog-tool 'verilog-compiler)
1432 (verilog-set-compile-command))
1434 :selected (equal verilog-tool `verilog-compiler)
1435 :help "When invoking compilation, compile Verilog source"]
1438 (setq verilog-tool 'verilog-preprocessor)
1439 (verilog-set-compile-command))
1441 :selected (equal verilog-tool `verilog-preprocessor)
1442 :help "When invoking compilation, preprocess Verilog source, see also `verilog-preprocess'"]
1445 ["Beginning of function" verilog-beg-of-defun
1447 :help "Move backward to the beginning of the current function or procedure"]
1448 ["End of function" verilog-end-of-defun
1450 :help "Move forward to the end of the current function or procedure"]
1451 ["Mark function" verilog-mark-defun
1453 :help "Mark the current Verilog function or procedure"]
1454 ["Goto function/module" verilog-goto-defun
1455 :help "Move to specified Verilog module/task/function"]
1456 ["Move to beginning of block" electric-verilog-backward-sexp
1457 :help "Move backward over one balanced expression"]
1458 ["Move to end of block" electric-verilog-forward-sexp
1459 :help "Move forward over one balanced expression"]
1462 ["Comment Region" verilog-comment-region
1463 :help "Put marked area into a comment"]
1464 ["UnComment Region" verilog-uncomment-region
1465 :help "Uncomment an area commented with Comment Region"]
1466 ["Multi-line comment insert" verilog-star-comment
1467 :help "Insert Verilog /* */ comment at point"]
1468 ["Lint error to comment" verilog-lint-off
1469 :help "Convert a Verilog linter warning line into a disable statement"]
1473 :help "Perform compilation-action (above) on the current buffer"]
1474 ["AUTO, Save, Compile" verilog-auto-save-compile
1475 :help "Recompute AUTOs, save buffer, and compile"]
1476 ["Next Compile Error" next-error
1477 :help "Visit next compilation error message and corresponding source code"]
1478 ["Ignore Lint Warning at point" verilog-lint-off
1479 :help "Convert a Verilog linter warning line into a disable statement"]
1481 ["Line up declarations around point" verilog-pretty-declarations
1482 :help "Line up declarations around point"]
1483 ["Line up equations around point" verilog-pretty-expr
1484 :help "Line up expressions around point"]
1485 ["Redo/insert comments on every end" verilog-label-be
1486 :help "Label matching begin ... end statements"]
1487 ["Expand [x:y] vector line" verilog-expand-vector
1488 :help "Take a signal vector on the current line and expand it to multiple lines"]
1489 ["Insert begin-end block" verilog-insert-block
1490 :help "Insert begin ... end"]
1491 ["Complete word" verilog-complete-word
1492 :help "Complete word at point"]
1494 ["Recompute AUTOs" verilog-auto
1495 :help "Expand AUTO meta-comment statements"]
1496 ["Kill AUTOs" verilog-delete-auto
1497 :help "Remove AUTO expansions"]
1498 ["Diff AUTOs" verilog-diff-auto
1499 :help "Show differences in AUTO expansions"]
1500 ["Inject AUTOs" verilog-inject-auto
1501 :help "Inject AUTOs into legacy non-AUTO buffer"]
1503 ["AUTO General" (describe-function 'verilog-auto)
1504 :help "Help introduction on AUTOs"]
1505 ["AUTO Library Flags" (describe-variable 'verilog-library-flags)
1506 :help "Help on verilog-library-flags"]
1507 ["AUTO Library Path" (describe-variable 'verilog-library-directories)
1508 :help "Help on verilog-library-directories"]
1509 ["AUTO Library Files" (describe-variable 'verilog-library-files)
1510 :help "Help on verilog-library-files"]
1511 ["AUTO Library Extensions" (describe-variable 'verilog-library-extensions)
1512 :help "Help on verilog-library-extensions"]
1513 ["AUTO `define Reading" (describe-function 'verilog-read-defines)
1514 :help "Help on reading `defines"]
1515 ["AUTO `include Reading" (describe-function 'verilog-read-includes)
1516 :help "Help on parsing `includes"]
1517 ["AUTOARG" (describe-function 'verilog-auto-arg)
1518 :help "Help on AUTOARG - declaring module port list"]
1519 ["AUTOASCIIENUM" (describe-function 'verilog-auto-ascii-enum)
1520 :help "Help on AUTOASCIIENUM - creating ASCII for enumerations"]
1521 ["AUTOASSIGNMODPORT" (describe-function 'verilog-auto-assign-modport)
1522 :help "Help on AUTOASSIGNMODPORT - creating assignments to/from modports"]
1523 ["AUTOINOUT" (describe-function 'verilog-auto-inout)
1524 :help "Help on AUTOINOUT - adding inouts from cells"]
1525 ["AUTOINOUTCOMP" (describe-function 'verilog-auto-inout-comp)
1526 :help "Help on AUTOINOUTCOMP - copying complemented i/o from another file"]
1527 ["AUTOINOUTIN" (describe-function 'verilog-auto-inout-in)
1528 :help "Help on AUTOINOUTIN - copying i/o from another file as all inputs"]
1529 ["AUTOINOUTMODPORT" (describe-function 'verilog-auto-inout-modport)
1530 :help "Help on AUTOINOUTMODPORT - copying i/o from an interface modport"]
1531 ["AUTOINOUTMODULE" (describe-function 'verilog-auto-inout-module)
1532 :help "Help on AUTOINOUTMODULE - copying i/o from another file"]
1533 ["AUTOINOUTPARAM" (describe-function 'verilog-auto-inout-param)
1534 :help "Help on AUTOINOUTPARAM - copying parameters from another file"]
1535 ["AUTOINPUT" (describe-function 'verilog-auto-input)
1536 :help "Help on AUTOINPUT - adding inputs from cells"]
1537 ["AUTOINSERTLISP" (describe-function 'verilog-auto-insert-lisp)
1538 :help "Help on AUTOINSERTLISP - insert text from a lisp function"]
1539 ["AUTOINSERTLAST" (describe-function 'verilog-auto-insert-last)
1540 :help "Help on AUTOINSERTLISPLAST - insert text from a lisp function"]
1541 ["AUTOINST" (describe-function 'verilog-auto-inst)
1542 :help "Help on AUTOINST - adding pins for cells"]
1543 ["AUTOINST (.*)" (describe-function 'verilog-auto-star)
1544 :help "Help on expanding Verilog-2001 .* pins"]
1545 ["AUTOINSTPARAM" (describe-function 'verilog-auto-inst-param)
1546 :help "Help on AUTOINSTPARAM - adding parameter pins to cells"]
1547 ["AUTOLOGIC" (describe-function 'verilog-auto-logic)
1548 :help "Help on AUTOLOGIC - declaring logic signals"]
1549 ["AUTOOUTPUT" (describe-function 'verilog-auto-output)
1550 :help "Help on AUTOOUTPUT - adding outputs from cells"]
1551 ["AUTOOUTPUTEVERY" (describe-function 'verilog-auto-output-every)
1552 :help "Help on AUTOOUTPUTEVERY - adding outputs of all signals"]
1553 ["AUTOREG" (describe-function 'verilog-auto-reg)
1554 :help "Help on AUTOREG - declaring registers for non-wires"]
1555 ["AUTOREGINPUT" (describe-function 'verilog-auto-reg-input)
1556 :help "Help on AUTOREGINPUT - declaring inputs for non-wires"]
1557 ["AUTORESET" (describe-function 'verilog-auto-reset)
1558 :help "Help on AUTORESET - resetting always blocks"]
1559 ["AUTOSENSE or AS" (describe-function 'verilog-auto-sense)
1560 :help "Help on AUTOSENSE - sensitivity lists for always blocks"]
1561 ["AUTOTIEOFF" (describe-function 'verilog-auto-tieoff)
1562 :help "Help on AUTOTIEOFF - tying off unused outputs"]
1563 ["AUTOUNDEF" (describe-function 'verilog-auto-undef)
1564 :help "Help on AUTOUNDEF - undefine all local defines"]
1565 ["AUTOUNUSED" (describe-function 'verilog-auto-unused)
1566 :help "Help on AUTOUNUSED - terminating unused inputs"]
1567 ["AUTOWIRE" (describe-function 'verilog-auto-wire)
1568 :help "Help on AUTOWIRE - declaring wires for cells"]
1571 ["Submit bug report" verilog-submit-bug-report
1572 :help "Submit via mail a bug report on verilog-mode.el"]
1573 ["Version and FAQ" verilog-faq
1574 :help "Show the current version, and where to get the FAQ etc"]
1575 ["Customize Verilog Mode..." verilog-customize
1576 :help "Customize variables and other settings used by Verilog-Mode"]
1577 ["Customize Verilog Fonts & Colors" verilog-font-customize
1578 :help "Customize fonts used by Verilog-Mode."])))
1581 verilog-stmt-menu verilog-mode-map "Menu for statement templates in Verilog."
1582 (verilog-easy-menu-filter
1584 ["Header" verilog-sk-header
1585 :help "Insert a header block at the top of file"]
1586 ["Comment" verilog-sk-comment
1587 :help "Insert a comment block"]
1589 ["Module" verilog-sk-module
1590 :help "Insert a module .. (/*AUTOARG*/);.. endmodule block"]
1591 ["OVM Class" verilog-sk-ovm-class
1592 :help "Insert an OVM class block"]
1593 ["UVM Object" verilog-sk-uvm-object
1594 :help "Insert an UVM object block"]
1595 ["UVM Component" verilog-sk-uvm-component
1596 :help "Insert an UVM component block"]
1597 ["Primitive" verilog-sk-primitive
1598 :help "Insert a primitive .. (.. );.. endprimitive block"]
1600 ["Input" verilog-sk-input
1601 :help "Insert an input declaration"]
1602 ["Output" verilog-sk-output
1603 :help "Insert an output declaration"]
1604 ["Inout" verilog-sk-inout
1605 :help "Insert an inout declaration"]
1606 ["Wire" verilog-sk-wire
1607 :help "Insert a wire declaration"]
1608 ["Reg" verilog-sk-reg
1609 :help "Insert a register declaration"]
1610 ["Define thing under point as a register" verilog-sk-define-signal
1611 :help "Define signal under point as a register at the top of the module"]
1613 ["Initial" verilog-sk-initial
1614 :help "Insert an initial begin .. end block"]
1615 ["Always" verilog-sk-always
1616 :help "Insert an always @(AS) begin .. end block"]
1617 ["Function" verilog-sk-function
1618 :help "Insert a function .. begin .. end endfunction block"]
1619 ["Task" verilog-sk-task
1620 :help "Insert a task .. begin .. end endtask block"]
1621 ["Specify" verilog-sk-specify
1622 :help "Insert a specify .. endspecify block"]
1623 ["Generate" verilog-sk-generate
1624 :help "Insert a generate .. endgenerate block"]
1626 ["Begin" verilog-sk-begin
1627 :help "Insert a begin .. end block"]
1629 :help "Insert an if (..) begin .. end block"]
1630 ["(if) else" verilog-sk-else-if
1631 :help "Insert an else if (..) begin .. end block"]
1632 ["For" verilog-sk-for
1633 :help "Insert a for (...) begin .. end block"]
1634 ["While" verilog-sk-while
1635 :help "Insert a while (...) begin .. end block"]
1636 ["Fork" verilog-sk-fork
1637 :help "Insert a fork begin .. end .. join block"]
1638 ["Repeat" verilog-sk-repeat
1639 :help "Insert a repeat (..) begin .. end block"]
1640 ["Case" verilog-sk-case
1641 :help "Insert a case block, prompting for details"]
1642 ["Casex" verilog-sk-casex
1643 :help "Insert a casex (...) item: begin.. end endcase block"]
1644 ["Casez" verilog-sk-casez
1645 :help "Insert a casez (...) item: begin.. end endcase block"])))
1647 (defvar verilog-mode-abbrev-table nil
1648 "Abbrev table in use in Verilog-mode buffers.")
1650 (define-abbrev-table 'verilog-mode-abbrev-table ())
1651 (verilog-define-abbrev verilog-mode-abbrev-table "class" "" 'verilog-sk-ovm-class)
1652 (verilog-define-abbrev verilog-mode-abbrev-table "always" "" 'verilog-sk-always)
1653 (verilog-define-abbrev verilog-mode-abbrev-table "begin" nil `verilog-sk-begin)
1654 (verilog-define-abbrev verilog-mode-abbrev-table "case" "" `verilog-sk-case)
1655 (verilog-define-abbrev verilog-mode-abbrev-table "for" "" `verilog-sk-for)
1656 (verilog-define-abbrev verilog-mode-abbrev-table "generate" "" `verilog-sk-generate)
1657 (verilog-define-abbrev verilog-mode-abbrev-table "initial" "" `verilog-sk-initial)
1658 (verilog-define-abbrev verilog-mode-abbrev-table "fork" "" `verilog-sk-fork)
1659 (verilog-define-abbrev verilog-mode-abbrev-table "module" "" `verilog-sk-module)
1660 (verilog-define-abbrev verilog-mode-abbrev-table "primitive" "" `verilog-sk-primitive)
1661 (verilog-define-abbrev verilog-mode-abbrev-table "repeat" "" `verilog-sk-repeat)
1662 (verilog-define-abbrev verilog-mode-abbrev-table "specify" "" `verilog-sk-specify)
1663 (verilog-define-abbrev verilog-mode-abbrev-table "task" "" `verilog-sk-task)
1664 (verilog-define-abbrev verilog-mode-abbrev-table "while" "" `verilog-sk-while)
1665 (verilog-define-abbrev verilog-mode-abbrev-table "casex" "" `verilog-sk-casex)
1666 (verilog-define-abbrev verilog-mode-abbrev-table "casez" "" `verilog-sk-casez)
1667 (verilog-define-abbrev verilog-mode-abbrev-table "if" "" `verilog-sk-if)
1668 (verilog-define-abbrev verilog-mode-abbrev-table "else if" "" `verilog-sk-else-if)
1669 (verilog-define-abbrev verilog-mode-abbrev-table "assign" "" `verilog-sk-assign)
1670 (verilog-define-abbrev verilog-mode-abbrev-table "function" "" `verilog-sk-function)
1671 (verilog-define-abbrev verilog-mode-abbrev-table "input" "" `verilog-sk-input)
1672 (verilog-define-abbrev verilog-mode-abbrev-table "output" "" `verilog-sk-output)
1673 (verilog-define-abbrev verilog-mode-abbrev-table "inout" "" `verilog-sk-inout)
1674 (verilog-define-abbrev verilog-mode-abbrev-table "wire" "" `verilog-sk-wire)
1675 (verilog-define-abbrev verilog-mode-abbrev-table "reg" "" `verilog-sk-reg)
1681 (defsubst verilog-within-string ()
1682 (nth 3 (parse-partial-sexp (point-at-bol) (point))))
1684 (defsubst verilog-string-match-fold (regexp string &optional start)
1685 "Like `string-match', but use `verilog-case-fold'.
1686 Return index of start of first match for REGEXP in STRING, or nil.
1687 Matching ignores case if `verilog-case-fold' is non-nil.
1688 If third arg START is non-nil, start search at that index in STRING."
1689 (let ((case-fold-search verilog-case-fold))
1690 (string-match regexp string start)))
1692 (defsubst verilog-string-replace-matches (from-string to-string fixedcase literal string)
1693 "Replace occurrences of FROM-STRING with TO-STRING.
1694 FIXEDCASE and LITERAL as in `replace-match'. STRING is what to replace.
1695 The case (verilog-string-replace-matches \"o\" \"oo\" nil nil \"foobar\")
1696 will break, as the o's continuously replace. xa -> x works ok though."
1697 ;; Hopefully soon to an Emacs built-in
1698 ;; Also note \ in the replacement prevent multiple replacements; IE
1699 ;; (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil "wire@_@")
1700 ;; Gives "wire\([0-9]+\)_@" not "wire\([0-9]+\)_\([0-9]+\)"
1702 (while (string-match from-string string start)
1703 (setq string (replace-match to-string fixedcase literal string)
1704 start (min (length string) (+ (match-beginning 0) (length to-string)))))
1707 (defsubst verilog-string-remove-spaces (string)
1708 "Remove spaces surrounding STRING."
1710 (setq string (verilog-string-replace-matches "^\\s-+" "" nil nil string))
1711 (setq string (verilog-string-replace-matches "\\s-+$" "" nil nil string))
1714 (defsubst verilog-re-search-forward (REGEXP BOUND NOERROR)
1715 ;; checkdoc-params: (REGEXP BOUND NOERROR)
1716 "Like `re-search-forward', but skips over match in comments or strings."
1717 (let ((mdata '(nil nil))) ; So match-end will return nil if no matches found
1719 (re-search-forward REGEXP BOUND NOERROR)
1720 (setq mdata (match-data))
1721 (and (verilog-skip-forward-comment-or-string)
1723 (setq mdata '(nil nil))
1727 (store-match-data mdata)
1730 (defsubst verilog-re-search-backward (REGEXP BOUND NOERROR)
1731 ;; checkdoc-params: (REGEXP BOUND NOERROR)
1732 "Like `re-search-backward', but skips over match in comments or strings."
1733 (let ((mdata '(nil nil))) ; So match-end will return nil if no matches found
1735 (re-search-backward REGEXP BOUND NOERROR)
1736 (setq mdata (match-data))
1737 (and (verilog-skip-backward-comment-or-string)
1739 (setq mdata '(nil nil))
1743 (store-match-data mdata)
1746 (defsubst verilog-re-search-forward-quick (regexp bound noerror)
1747 "Like `verilog-re-search-forward', including use of REGEXP BOUND and NOERROR,
1748 but trashes match data and is faster for REGEXP that doesn't match often.
1749 This uses `verilog-scan' and text properties to ignore comments,
1750 so there may be a large up front penalty for the first search."
1752 (while (and (not pt)
1753 (re-search-forward regexp bound noerror))
1754 (if (verilog-inside-comment-or-string-p)
1755 (re-search-forward "[/\"\n]" nil t) ; Only way a comment or quote can end
1756 (setq pt (match-end 0))))
1759 (defsubst verilog-re-search-backward-quick (regexp bound noerror)
1760 ;; checkdoc-params: (REGEXP BOUND NOERROR)
1761 "Like `verilog-re-search-backward', including use of REGEXP BOUND and NOERROR,
1762 but trashes match data and is faster for REGEXP that doesn't match often.
1763 This uses `verilog-scan' and text properties to ignore comments,
1764 so there may be a large up front penalty for the first search."
1766 (while (and (not pt)
1767 (re-search-backward regexp bound noerror))
1768 (if (verilog-inside-comment-or-string-p)
1769 (re-search-backward "[/\"]" nil t) ; Only way a comment or quote can begin
1770 (setq pt (match-beginning 0))))
1773 (defsubst verilog-re-search-forward-substr (substr regexp bound noerror)
1774 "Like `re-search-forward', but first search for SUBSTR constant.
1775 Then searched for the normal REGEXP (which contains SUBSTR), with given
1776 BOUND and NOERROR. The REGEXP must fit within a single line.
1777 This speeds up complicated regexp matches."
1778 ;; Problem with overlap: search-forward BAR then FOOBARBAZ won't match.
1779 ;; thus require matches to be on one line, and use beginning-of-line.
1781 (while (and (not done)
1782 (search-forward substr bound noerror))
1785 (setq done (re-search-forward regexp (point-at-eol) noerror)))
1786 (unless (and (<= (match-beginning 0) (point))
1787 (>= (match-end 0) (point)))
1789 (when done (goto-char done))
1791 ;;(verilog-re-search-forward-substr "-end" "get-end-of" nil t) ; -end (test bait)
1793 (defsubst verilog-re-search-backward-substr (substr regexp bound noerror)
1794 "Like `re-search-backward', but first search for SUBSTR constant.
1795 Then searched for the normal REGEXP (which contains SUBSTR), with given
1796 BOUND and NOERROR. The REGEXP must fit within a single line.
1797 This speeds up complicated regexp matches."
1798 ;; Problem with overlap: search-backward BAR then FOOBARBAZ won't match.
1799 ;; thus require matches to be on one line, and use beginning-of-line.
1801 (while (and (not done)
1802 (search-backward substr bound noerror))
1805 (setq done (re-search-backward regexp (point-at-bol) noerror)))
1806 (unless (and (<= (match-beginning 0) (point))
1807 (>= (match-end 0) (point)))
1809 (when done (goto-char done))
1811 ;;(verilog-re-search-backward-substr "-end" "get-end-of" nil t) ; -end (test bait)
1813 (defun verilog-delete-trailing-whitespace ()
1814 "Delete trailing spaces or tabs, but not newlines nor linefeeds.
1815 Also add missing final newline.
1817 To call this from the command line, see \\[verilog-batch-diff-auto].
1819 To call on \\[verilog-auto], set `verilog-auto-delete-trailing-whitespace'."
1820 ;; Similar to `delete-trailing-whitespace' but that's not present in XEmacs
1822 (goto-char (point-min))
1823 (while (re-search-forward "[ \t]+$" nil t) ; Not syntactic WS as no formfeed
1824 (replace-match "" nil nil))
1825 (goto-char (point-max))
1826 (unless (bolp) (insert "\n"))))
1828 (defvar compile-command)
1829 (defvar create-lockfiles) ; Emacs 24
1831 ;; compilation program
1832 (defun verilog-set-compile-command ()
1833 "Function to compute shell command to compile Verilog.
1835 This reads `verilog-tool' and sets `compile-command'. This specifies the
1836 program that executes when you type \\[compile] or
1837 \\[verilog-auto-save-compile].
1839 By default `verilog-tool' uses a Makefile if one exists in the
1840 current directory. If not, it is set to the `verilog-linter',
1841 `verilog-compiler', `verilog-coverage', `verilog-preprocessor',
1842 or `verilog-simulator' variables, as selected with the Verilog ->
1843 \"Choose Compilation Action\" menu.
1845 You should set `verilog-tool' or the other variables to the path and
1846 arguments for your Verilog simulator. For example:
1849 \"(cd /tmp; surecov %s)\".
1851 In the former case, the path to the current buffer is concat'ed to the
1852 value of `verilog-tool'; in the later, the path to the current buffer is
1853 substituted for the %s.
1855 Where __FLAGS__ appears in the string `verilog-current-flags'
1856 will be substituted.
1858 Where __FILE__ appears in the string, the variable
1859 `buffer-file-name' of the current buffer, without the directory
1860 portion, will be substituted."
1863 ((or (file-exists-p "makefile") ;If there is a makefile, use it
1864 (file-exists-p "Makefile"))
1865 (set (make-local-variable 'compile-command) "make "))
1867 (set (make-local-variable 'compile-command)
1869 (if (string-match "%s" (eval verilog-tool))
1870 (format (eval verilog-tool) (or buffer-file-name ""))
1871 (concat (eval verilog-tool) " " (or buffer-file-name "")))
1873 (verilog-modify-compile-command))
1875 (defun verilog-expand-command (command)
1876 "Replace meta-information in COMMAND and return it.
1877 Where __FLAGS__ appears in the string `verilog-current-flags'
1878 will be substituted. Where __FILE__ appears in the string, the
1879 current buffer's file-name, without the directory portion, will
1881 (setq command (verilog-string-replace-matches
1882 ;; Note \\b only works if under verilog syntax table
1883 "\\b__FLAGS__\\b" (verilog-current-flags)
1885 (setq command (verilog-string-replace-matches
1886 "\\b__FILE__\\b" (file-name-nondirectory
1887 (or (buffer-file-name) ""))
1891 (defun verilog-modify-compile-command ()
1892 "Update `compile-command' using `verilog-expand-command'."
1894 (stringp compile-command)
1895 (string-match "\\b\\(__FLAGS__\\|__FILE__\\)\\b" compile-command))
1896 (set (make-local-variable 'compile-command)
1897 (verilog-expand-command compile-command))))
1899 (if (featurep 'xemacs)
1900 ;; Following code only gets called from compilation-mode-hook on XEmacs to add error handling.
1901 (defun verilog-error-regexp-add-xemacs ()
1902 "Teach XEmacs about verilog errors.
1903 Called by `compilation-mode-hook'. This allows \\[next-error] to
1906 (if (boundp 'compilation-error-regexp-systems-alist)
1908 (not (equal compilation-error-regexp-systems-list 'all))
1909 (not (member compilation-error-regexp-systems-list 'verilog)))
1910 (push 'verilog compilation-error-regexp-systems-list)))
1911 (if (boundp 'compilation-error-regexp-alist-alist)
1912 (if (not (assoc 'verilog compilation-error-regexp-alist-alist))
1913 (setcdr compilation-error-regexp-alist-alist
1914 (cons verilog-error-regexp-xemacs-alist
1915 (cdr compilation-error-regexp-alist-alist)))))
1916 (if (boundp 'compilation-font-lock-keywords)
1918 (set (make-local-variable 'compilation-font-lock-keywords)
1919 verilog-error-font-lock-keywords)
1920 (font-lock-set-defaults)))
1921 ;; Need to re-run compilation-error-regexp builder
1922 (if (fboundp 'compilation-build-compilation-error-regexp-alist)
1923 (compilation-build-compilation-error-regexp-alist))
1926 ;; Following code only gets called from compilation-mode-hook on Emacs to add error handling.
1927 (defun verilog-error-regexp-add-emacs ()
1928 "Tell Emacs compile that we are Verilog.
1929 Called by `compilation-mode-hook'. This allows \\[next-error] to
1932 (when (boundp 'compilation-error-regexp-alist-alist)
1933 (when (not (assoc 'verilog-xl-1 compilation-error-regexp-alist-alist))
1936 (push (car item) compilation-error-regexp-alist)
1937 (push item compilation-error-regexp-alist-alist))
1938 verilog-error-regexp-emacs-alist))))
1940 (if (featurep 'xemacs) (add-hook 'compilation-mode-hook 'verilog-error-regexp-add-xemacs))
1941 (if (featurep 'emacs) (add-hook 'compilation-mode-hook 'verilog-error-regexp-add-emacs))
1943 (defconst verilog-compiler-directives
1946 ;; compiler directives, from IEEE 1800-2012 section 22.1
1947 "`__FILE__" "`__LINE" "`begin_keywords" "`celldefine" "`default_nettype"
1948 "`define" "`else" "`elsif" "`end_keywords" "`endcelldefine" "`endif"
1949 "`ifdef" "`ifndef" "`include" "`line" "`nounconnected_drive" "`pragma"
1950 "`resetall" "`timescale" "`unconnected_drive" "`undef" "`undefineall"
1951 ;; compiler directives not covered by IEEE 1800
1952 "`case" "`default" "`endfor" "`endprotect" "`endswitch" "`endwhile" "`for"
1953 "`format" "`if" "`let" "`protect" "`switch" "`timescale" "`time_scale"
1956 "List of Verilog compiler directives.")
1958 (defconst verilog-directive-re
1959 (verilog-regexp-words verilog-compiler-directives))
1961 (defconst verilog-directive-re-1
1962 (concat "[ \t]*" verilog-directive-re))
1964 (defconst verilog-directive-begin
1965 "\\<`\\(for\\|i\\(f\\|fdef\\|fndef\\)\\|switch\\|while\\)\\>")
1967 (defconst verilog-directive-middle
1968 "\\<`\\(else\\|elsif\\|default\\|case\\)\\>")
1970 (defconst verilog-directive-end
1971 "`\\(endfor\\|endif\\|endswitch\\|endwhile\\)\\>")
1973 (defconst verilog-ovm-begin-re
1977 "`ovm_component_utils_begin"
1978 "`ovm_component_param_utils_begin"
1979 "`ovm_field_utils_begin"
1980 "`ovm_object_utils_begin"
1981 "`ovm_object_param_utils_begin"
1982 "`ovm_sequence_utils_begin"
1983 "`ovm_sequencer_utils_begin"
1986 (defconst verilog-ovm-end-re
1990 "`ovm_component_utils_end"
1991 "`ovm_field_utils_end"
1992 "`ovm_object_utils_end"
1993 "`ovm_sequence_utils_end"
1994 "`ovm_sequencer_utils_end"
1997 (defconst verilog-uvm-begin-re
2001 "`uvm_component_utils_begin"
2002 "`uvm_component_param_utils_begin"
2003 "`uvm_field_utils_begin"
2004 "`uvm_object_utils_begin"
2005 "`uvm_object_param_utils_begin"
2006 "`uvm_sequence_utils_begin"
2007 "`uvm_sequencer_utils_begin"
2010 (defconst verilog-uvm-end-re
2014 "`uvm_component_utils_end"
2015 "`uvm_field_utils_end"
2016 "`uvm_object_utils_end"
2017 "`uvm_sequence_utils_end"
2018 "`uvm_sequencer_utils_end"
2021 (defconst verilog-vmm-begin-re
2025 "`vmm_data_member_begin"
2026 "`vmm_env_member_begin"
2027 "`vmm_scenario_member_begin"
2028 "`vmm_subenv_member_begin"
2029 "`vmm_xactor_member_begin"
2032 (defconst verilog-vmm-end-re
2036 "`vmm_data_member_end"
2037 "`vmm_env_member_end"
2038 "`vmm_scenario_member_end"
2039 "`vmm_subenv_member_end"
2040 "`vmm_xactor_member_end"
2043 (defconst verilog-vmm-statement-re
2047 "`vmm_\\(data\\|env\\|scenario\\|subenv\\|xactor\\)_member_\\(scalar\\|string\\|enum\\|vmm_data\\|channel\\|xactor\\|subenv\\|user_defined\\)\\(_array\\)?"
2048 ;; "`vmm_xactor_member_enum_array"
2049 ;; "`vmm_xactor_member_scalar_array"
2050 ;; "`vmm_xactor_member_scalar"
2053 (defconst verilog-ovm-statement-re
2062 "`ovm_analysis_imp_decl"
2063 "`ovm_blocking_get_imp_decl"
2064 "`ovm_blocking_get_peek_imp_decl"
2065 "`ovm_blocking_master_imp_decl"
2066 "`ovm_blocking_peek_imp_decl"
2067 "`ovm_blocking_put_imp_decl"
2068 "`ovm_blocking_slave_imp_decl"
2069 "`ovm_blocking_transport_imp_decl"
2070 "`ovm_component_registry"
2071 "`ovm_component_registry_param"
2072 "`ovm_component_utils"
2075 "`ovm_declare_sequence_lib"
2082 "`ovm_field_aa_int_byte"
2083 "`ovm_field_aa_int_byte_unsigned"
2084 "`ovm_field_aa_int_int"
2085 "`ovm_field_aa_int_int_unsigned"
2086 "`ovm_field_aa_int_integer"
2087 "`ovm_field_aa_int_integer_unsigned"
2088 "`ovm_field_aa_int_key"
2089 "`ovm_field_aa_int_longint"
2090 "`ovm_field_aa_int_longint_unsigned"
2091 "`ovm_field_aa_int_shortint"
2092 "`ovm_field_aa_int_shortint_unsigned"
2093 "`ovm_field_aa_int_string"
2094 "`ovm_field_aa_object_int"
2095 "`ovm_field_aa_object_string"
2096 "`ovm_field_aa_string_int"
2097 "`ovm_field_aa_string_string"
2098 "`ovm_field_array_int"
2099 "`ovm_field_array_object"
2100 "`ovm_field_array_string"
2105 "`ovm_field_queue_int"
2106 "`ovm_field_queue_object"
2107 "`ovm_field_queue_string"
2108 "`ovm_field_sarray_int"
2113 "`ovm_get_peek_imp_decl"
2120 "`ovm_master_imp_decl"
2122 "`ovm_non_blocking_transport_imp_decl"
2123 "`ovm_nonblocking_get_imp_decl"
2124 "`ovm_nonblocking_get_peek_imp_decl"
2125 "`ovm_nonblocking_master_imp_decl"
2126 "`ovm_nonblocking_peek_imp_decl"
2127 "`ovm_nonblocking_put_imp_decl"
2128 "`ovm_nonblocking_slave_imp_decl"
2129 "`ovm_object_registry"
2130 "`ovm_object_registry_param"
2132 "`ovm_peek_imp_decl"
2133 "`ovm_phase_func_decl"
2134 "`ovm_phase_task_decl"
2135 "`ovm_print_aa_int_object"
2136 "`ovm_print_aa_string_int"
2137 "`ovm_print_aa_string_object"
2138 "`ovm_print_aa_string_string"
2139 "`ovm_print_array_int"
2140 "`ovm_print_array_object"
2141 "`ovm_print_array_string"
2142 "`ovm_print_object_queue"
2143 "`ovm_print_queue_int"
2144 "`ovm_print_string_queue"
2147 "`ovm_rand_send_with"
2149 "`ovm_sequence_utils"
2150 "`ovm_slave_imp_decl"
2151 "`ovm_transport_imp_decl"
2152 "`ovm_update_sequence_lib"
2153 "`ovm_update_sequence_lib_and_item"
2156 "`static_message") nil )))
2158 (defconst verilog-uvm-statement-re
2163 "`uvm_analysis_imp_decl"
2164 "`uvm_blocking_get_imp_decl"
2165 "`uvm_blocking_get_peek_imp_decl"
2166 "`uvm_blocking_master_imp_decl"
2167 "`uvm_blocking_peek_imp_decl"
2168 "`uvm_blocking_put_imp_decl"
2169 "`uvm_blocking_slave_imp_decl"
2170 "`uvm_blocking_transport_imp_decl"
2171 "`uvm_component_param_utils"
2172 "`uvm_component_registry"
2173 "`uvm_component_registry_param"
2174 "`uvm_component_utils"
2177 "`uvm_create_seq" ; Undocumented in 1.1
2178 "`uvm_declare_p_sequencer"
2179 "`uvm_declare_sequence_lib" ; Deprecated in 1.1
2182 "`uvm_do_callbacks_exit_on"
2183 "`uvm_do_obj_callbacks"
2184 "`uvm_do_obj_callbacks_exit_on"
2187 "`uvm_do_on_pri_with"
2191 "`uvm_do_seq" ; Undocumented in 1.1
2192 "`uvm_do_seq_with" ; Undocumented in 1.1
2195 "`uvm_error_context"
2197 "`uvm_fatal_context"
2198 "`uvm_field_aa_int_byte"
2199 "`uvm_field_aa_int_byte_unsigned"
2200 "`uvm_field_aa_int_enum"
2201 "`uvm_field_aa_int_int"
2202 "`uvm_field_aa_int_int_unsigned"
2203 "`uvm_field_aa_int_integer"
2204 "`uvm_field_aa_int_integer_unsigned"
2205 "`uvm_field_aa_int_key"
2206 "`uvm_field_aa_int_longint"
2207 "`uvm_field_aa_int_longint_unsigned"
2208 "`uvm_field_aa_int_shortint"
2209 "`uvm_field_aa_int_shortint_unsigned"
2210 "`uvm_field_aa_int_string"
2211 "`uvm_field_aa_object_int"
2212 "`uvm_field_aa_object_string"
2213 "`uvm_field_aa_string_int"
2214 "`uvm_field_aa_string_string"
2215 "`uvm_field_array_enum"
2216 "`uvm_field_array_int"
2217 "`uvm_field_array_object"
2218 "`uvm_field_array_string"
2223 "`uvm_field_queue_enum"
2224 "`uvm_field_queue_int"
2225 "`uvm_field_queue_object"
2226 "`uvm_field_queue_string"
2228 "`uvm_field_sarray_enum"
2229 "`uvm_field_sarray_int"
2230 "`uvm_field_sarray_object"
2231 "`uvm_field_sarray_string"
2234 "`uvm_file" ; Undocumented in 1.1, use `__FILE__
2236 "`uvm_get_peek_imp_decl"
2239 "`uvm_line" ; Undocumented in 1.1, use `__LINE__
2240 "`uvm_master_imp_decl"
2241 "`uvm_non_blocking_transport_imp_decl" ; Deprecated in 1.1
2242 "`uvm_nonblocking_get_imp_decl"
2243 "`uvm_nonblocking_get_peek_imp_decl"
2244 "`uvm_nonblocking_master_imp_decl"
2245 "`uvm_nonblocking_peek_imp_decl"
2246 "`uvm_nonblocking_put_imp_decl"
2247 "`uvm_nonblocking_slave_imp_decl"
2248 "`uvm_nonblocking_transport_imp_decl"
2249 "`uvm_object_param_utils"
2250 "`uvm_object_registry"
2251 "`uvm_object_registry_param" ; Undocumented in 1.1
2265 "`uvm_peek_imp_decl"
2268 "`uvm_rand_send_pri"
2269 "`uvm_rand_send_pri_with"
2270 "`uvm_rand_send_with"
2271 "`uvm_record_attribute"
2276 "`uvm_sequence_utils" ; Deprecated in 1.1
2277 "`uvm_set_super_type"
2278 "`uvm_slave_imp_decl"
2279 "`uvm_transport_imp_decl"
2281 "`uvm_unpack_arrayN"
2287 "`uvm_unpack_queueN"
2289 "`uvm_unpack_sarray"
2290 "`uvm_unpack_sarrayN"
2291 "`uvm_unpack_string"
2292 "`uvm_update_sequence_lib" ; Deprecated in 1.1
2293 "`uvm_update_sequence_lib_and_item" ; Deprecated in 1.1
2295 "`uvm_warning_context") nil )))
2299 ;; Regular expressions used to calculate indent, etc.
2301 (defconst verilog-symbol-re "\\<[a-zA-Z_][a-zA-Z_0-9.]*\\>")
2308 (defconst verilog-assignment-operator-re
2312 ;; blocking assignment_operator
2313 "=" "+=" "-=" "*=" "/=" "%=" "&=" "|=" "^=" "<<=" ">>=" "<<<=" ">>>="
2314 ;; non blocking assignment operator
2317 "==" "!=" "===" "!==" "<=" ">=" "==?" "!=?" "<->"
2321 "|->" "|=>" "#-#" "#=#"
2322 ;; distribution weighting
2326 (defconst verilog-assignment-operation-re
2328 ;; "\\(^\\s-*[A-Za-z0-9_]+\\(\\[\\([A-Za-z0-9_]+\\)\\]\\)*\\s-*\\)"
2329 ;; "\\(^\\s-*[^=<>+-*/%&|^:\\s-]+[^=<>+-*/%&|^\n]*?\\)"
2330 "\\(^.*?\\)" "\\B" verilog-assignment-operator-re "\\B" ))
2332 (defconst verilog-label-re (concat verilog-symbol-re "\\s-*:\\s-*"))
2333 (defconst verilog-property-re
2334 (concat "\\(" verilog-label-re "\\)?"
2335 ;; "\\(assert\\|assume\\|cover\\)\\s-+property\\>"
2336 "\\(\\(assert\\|assume\\|cover\\)\\>\\s-+\\<property\\>\\)\\|\\(assert\\)"))
2338 (defconst verilog-no-indent-begin-re
2340 (verilog-regexp-words
2341 '("always" "always_comb" "always_ff" "always_latch" "initial" "final" ; procedural blocks
2342 "if" "else" ; conditional statements
2343 "while" "for" "foreach" "repeat" "do" "forever" )))) ; loop statements
2345 (defconst verilog-ends-re
2346 ;; Parenthesis indicate type of keyword found
2348 "\\(\\<else\\>\\)\\|" ; 1
2349 "\\(\\<if\\>\\)\\|" ; 2
2350 "\\(\\<assert\\>\\)\\|" ; 3
2351 "\\(\\<end\\>\\)\\|" ; 3.1
2352 "\\(\\<endcase\\>\\)\\|" ; 4
2353 "\\(\\<endfunction\\>\\)\\|" ; 5
2354 "\\(\\<endtask\\>\\)\\|" ; 6
2355 "\\(\\<endspecify\\>\\)\\|" ; 7
2356 "\\(\\<endtable\\>\\)\\|" ; 8
2357 "\\(\\<endgenerate\\>\\)\\|" ; 9
2358 "\\(\\<join\\(_any\\|_none\\)?\\>\\)\\|" ; 10
2359 "\\(\\<endclass\\>\\)\\|" ; 11
2360 "\\(\\<endgroup\\>\\)\\|" ; 12
2362 "\\(\\<`vmm_data_member_end\\>\\)\\|"
2363 "\\(\\<`vmm_env_member_end\\>\\)\\|"
2364 "\\(\\<`vmm_scenario_member_end\\>\\)\\|"
2365 "\\(\\<`vmm_subenv_member_end\\>\\)\\|"
2366 "\\(\\<`vmm_xactor_member_end\\>\\)\\|"
2368 "\\(\\<`ovm_component_utils_end\\>\\)\\|"
2369 "\\(\\<`ovm_field_utils_end\\>\\)\\|"
2370 "\\(\\<`ovm_object_utils_end\\>\\)\\|"
2371 "\\(\\<`ovm_sequence_utils_end\\>\\)\\|"
2372 "\\(\\<`ovm_sequencer_utils_end\\>\\)"
2374 "\\(\\<`uvm_component_utils_end\\>\\)\\|"
2375 "\\(\\<`uvm_field_utils_end\\>\\)\\|"
2376 "\\(\\<`uvm_object_utils_end\\>\\)\\|"
2377 "\\(\\<`uvm_sequence_utils_end\\>\\)\\|"
2378 "\\(\\<`uvm_sequencer_utils_end\\>\\)"
2381 (defconst verilog-auto-end-comment-lines-re
2382 ;; Matches to names in this list cause auto-end-commenting
2384 verilog-directive-re "\\)\\|\\("
2386 (verilog-regexp-words
2415 ;; NOTE: verilog-leap-to-head expects that verilog-end-block-re and
2416 ;; verilog-end-block-ordered-re matches exactly the same strings.
2417 (defconst verilog-end-block-ordered-re
2418 ;; Parenthesis indicate type of keyword found
2419 (concat "\\(\\<endcase\\>\\)\\|" ; 1
2420 "\\(\\<end\\>\\)\\|" ; 2
2421 "\\(\\<end" ; 3, but not used
2422 "\\(" ; 4, but not used
2423 "\\(function\\)\\|" ; 5
2425 "\\(module\\)\\|" ; 7
2426 "\\(primitive\\)\\|" ; 8
2427 "\\(interface\\)\\|" ; 9
2428 "\\(package\\)\\|" ; 10
2429 "\\(class\\)\\|" ; 11
2430 "\\(group\\)\\|" ; 12
2431 "\\(program\\)\\|" ; 13
2432 "\\(sequence\\)\\|" ; 14
2433 "\\(clocking\\)\\|" ; 15
2434 "\\(property\\)\\|" ; 16
2436 (defconst verilog-end-block-re
2438 (verilog-regexp-words
2440 `("end" ; closes begin
2441 "endcase" ; closes any of case, casex casez or randcase
2442 "join" "join_any" "join_none" ; closes fork
2457 "`ovm_component_utils_end"
2458 "`ovm_field_utils_end"
2459 "`ovm_object_utils_end"
2460 "`ovm_sequence_utils_end"
2461 "`ovm_sequencer_utils_end"
2463 "`uvm_component_utils_end"
2464 "`uvm_field_utils_end"
2465 "`uvm_object_utils_end"
2466 "`uvm_sequence_utils_end"
2467 "`uvm_sequencer_utils_end"
2469 "`vmm_data_member_end"
2470 "`vmm_env_member_end"
2471 "`vmm_scenario_member_end"
2472 "`vmm_subenv_member_end"
2473 "`vmm_xactor_member_end"
2477 (defconst verilog-endcomment-reason-re
2478 ;; Parenthesis indicate type of keyword found
2480 "\\(\\<begin\\>\\)\\|" ; 1
2481 "\\(\\<else\\>\\)\\|" ; 2
2482 "\\(\\<end\\>\\s-+\\<else\\>\\)\\|" ; 3
2483 "\\(\\<always\\(?:_ff\\)?\\>\\(?:[ \t]*@\\)\\)\\|" ; 4 (matches always or always_ff w/ @...)
2484 "\\(\\<always\\(?:_comb\\|_latch\\)?\\>\\)\\|" ; 5 (matches always, always_comb, always_latch w/o @...)
2485 "\\(\\<fork\\>\\)\\|" ; 7
2487 verilog-property-re "\\|"
2488 "\\(\\(" verilog-label-re "\\)?\\<assert\\>\\)\\|"
2489 "\\(\\<clocking\\>\\)\\|"
2490 "\\(\\<task\\>\\)\\|"
2491 "\\(\\<function\\>\\)\\|"
2492 "\\(\\<initial\\>\\)\\|"
2493 "\\(\\<interface\\>\\)\\|"
2494 "\\(\\<package\\>\\)\\|"
2495 "\\(\\<final\\>\\)\\|"
2497 "\\(\\<while\\>\\)\\|\\(\\<do\\>\\)\\|"
2498 "\\(\\<for\\(ever\\|each\\)?\\>\\)\\|"
2499 "\\(\\<repeat\\>\\)\\|\\(\\<wait\\>\\)\\|"
2502 (defconst verilog-named-block-re "begin[ \t]*:")
2504 ;; These words begin a block which can occur inside a module which should be indented,
2505 ;; and closed with the respective word from the end-block list
2507 (defconst verilog-beg-block-re
2509 (verilog-regexp-words
2511 "case" "casex" "casez" "randcase"
2521 "`ovm_component_utils_begin"
2522 "`ovm_component_param_utils_begin"
2523 "`ovm_field_utils_begin"
2524 "`ovm_object_utils_begin"
2525 "`ovm_object_param_utils_begin"
2526 "`ovm_sequence_utils_begin"
2527 "`ovm_sequencer_utils_begin"
2529 "`uvm_component_utils_begin"
2530 "`uvm_component_param_utils_begin"
2531 "`uvm_field_utils_begin"
2532 "`uvm_object_utils_begin"
2533 "`uvm_object_param_utils_begin"
2534 "`uvm_sequence_utils_begin"
2535 "`uvm_sequencer_utils_begin"
2537 "`vmm_data_member_begin"
2538 "`vmm_env_member_begin"
2539 "`vmm_scenario_member_begin"
2540 "`vmm_subenv_member_begin"
2541 "`vmm_xactor_member_begin"
2543 ;; These are the same words, in a specific order in the regular
2544 ;; expression so that matching will work nicely for
2545 ;; verilog-forward-sexp and verilog-calc-indent
2546 (defconst verilog-beg-block-re-ordered
2547 ( concat "\\(\\<begin\\>\\)" ;1
2548 "\\|\\(\\<randcase\\>\\|\\(\\<unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\>\\)" ; 2,3
2549 "\\|\\(\\(\\<disable\\>\\s-+\\|\\<wait\\>\\s-+\\)?fork\\>\\)" ;4,5
2550 "\\|\\(\\<class\\>\\)" ;6
2551 "\\|\\(\\<table\\>\\)" ;7
2552 "\\|\\(\\<specify\\>\\)" ;8
2553 "\\|\\(\\<function\\>\\)" ;9
2554 "\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)*\\<function\\>\\)" ;10
2555 "\\|\\(\\<task\\>\\)" ;14
2556 "\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)*\\<task\\>\\)" ;15
2557 "\\|\\(\\<generate\\>\\)" ;18
2558 "\\|\\(\\<covergroup\\>\\)" ;16 20
2559 "\\|\\(\\(\\(\\<cover\\>\\s-+\\)\\|\\(\\<assert\\>\\s-+\\)\\)*\\<property\\>\\)" ;17 21
2560 "\\|\\(\\<\\(rand\\)?sequence\\>\\)" ;21 25
2561 "\\|\\(\\<clocking\\>\\)" ;22 27
2562 "\\|\\(\\<`[ou]vm_[a-z_]+_begin\\>\\)" ;28
2563 "\\|\\(\\<`vmm_[a-z_]+_member_begin\\>\\)"
2567 (defconst verilog-end-block-ordered-rry
2568 [ "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
2569 "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)"
2570 "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
2571 "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)"
2572 "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)"
2573 "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)"
2574 "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)"
2575 "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)"
2576 "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)"
2577 "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)"
2578 "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)"
2579 "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)"
2580 "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)"
2583 (defconst verilog-nameable-item-re
2585 (verilog-regexp-words
2588 "join" "join_any" "join_none"
2610 (defconst verilog-declaration-opener
2612 (verilog-regexp-words
2613 `("module" "begin" "task" "function"))))
2615 (defconst verilog-declaration-prefix-re
2617 (verilog-regexp-words
2620 "inout" "input" "output" "ref"
2622 "const" "static" "protected" "local"
2624 "localparam" "parameter" "var"
2628 (defconst verilog-declaration-core-re
2630 (verilog-regexp-words
2632 ;; port direction (by themselves)
2633 "inout" "input" "output"
2634 ;; integer_atom_type
2635 "byte" "shortint" "int" "longint" "integer" "time"
2636 ;; integer_vector_type
2639 "shortreal" "real" "realtime"
2641 "supply0" "supply1" "tri" "triand" "trior" "trireg" "tri0" "tri1" "uwire" "wire" "wand" "wor"
2643 "string" "event" "chandle" "virtual" "enum" "genvar"
2646 "mailbox" "semaphore"
2648 (defconst verilog-declaration-re
2649 (concat "\\(" verilog-declaration-prefix-re "\\s-*\\)?" verilog-declaration-core-re))
2650 (defconst verilog-range-re "\\(\\[[^]]*\\]\\s-*\\)+")
2651 (defconst verilog-optional-signed-re "\\s-*\\(\\(un\\)?signed\\)?")
2652 (defconst verilog-optional-signed-range-re
2654 "\\s-*\\(\\<\\(reg\\|wire\\)\\>\\s-*\\)?\\(\\<\\(un\\)?signed\\>\\s-*\\)?\\(" verilog-range-re "\\)?"))
2655 (defconst verilog-macroexp-re "`\\sw+")
2657 (defconst verilog-delay-re "#\\s-*\\(\\([0-9_]+\\('s?[hdxbo][0-9a-fA-F_xz]+\\)?\\)\\|\\(([^()]*)\\)\\|\\(\\sw+\\)\\)")
2658 (defconst verilog-declaration-re-2-no-macro
2659 (concat "\\s-*" verilog-declaration-re
2660 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
2662 (defconst verilog-declaration-re-2-macro
2663 (concat "\\s-*" verilog-declaration-re
2664 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
2665 "\\|\\(" verilog-macroexp-re "\\)"
2667 (defconst verilog-declaration-re-1-macro
2668 (concat "^" verilog-declaration-re-2-macro))
2670 (defconst verilog-declaration-re-1-no-macro (concat "^" verilog-declaration-re-2-no-macro))
2672 (defconst verilog-defun-re
2673 (eval-when-compile (verilog-regexp-words `("macromodule" "module" "class" "program" "interface" "package" "primitive" "config"))))
2674 (defconst verilog-end-defun-re
2675 (eval-when-compile (verilog-regexp-words `("endmodule" "endclass" "endprogram" "endinterface" "endpackage" "endprimitive" "endconfig"))))
2676 (defconst verilog-zero-indent-re
2677 (concat verilog-defun-re "\\|" verilog-end-defun-re))
2678 (defconst verilog-inst-comment-re
2679 (eval-when-compile (verilog-regexp-words `("Outputs" "Inouts" "Inputs" "Interfaces" "Interfaced"))))
2681 (defconst verilog-behavioral-block-beg-re
2682 (eval-when-compile (verilog-regexp-words `("initial" "final" "always" "always_comb" "always_latch" "always_ff"
2683 "function" "task"))))
2684 (defconst verilog-coverpoint-re "\\w+\\s*:\\s*\\(coverpoint\\|cross\\constraint\\)" )
2685 (defconst verilog-in-constraint-re ; keywords legal in constraint blocks starting a statement/block
2686 (eval-when-compile (verilog-regexp-words `("if" "else" "solve" "foreach"))))
2688 (defconst verilog-indent-re
2690 (verilog-regexp-words
2693 "always" "always_latch" "always_ff" "always_comb"
2695 ;; "unique" "priority"
2696 "case" "casex" "casez" "randcase" "endcase"
2698 "clocking" "endclocking"
2699 "config" "endconfig"
2700 "covergroup" "endgroup"
2701 "fork" "join" "join_any" "join_none"
2702 "function" "endfunction"
2704 "generate" "endgenerate"
2706 "interface" "endinterface"
2707 "module" "macromodule" "endmodule"
2708 "package" "endpackage"
2709 "primitive" "endprimitive"
2710 "program" "endprogram"
2711 "property" "endproperty"
2712 "sequence" "randsequence" "endsequence"
2713 "specify" "endspecify"
2720 "`if" "`ifdef" "`ifndef" "`else" "`elsif" "`endif"
2721 "`while" "`endwhile"
2726 "`protect" "`endprotect"
2727 "`switch" "`endswitch"
2731 "`ovm_component_utils_begin"
2732 "`ovm_component_param_utils_begin"
2733 "`ovm_field_utils_begin"
2734 "`ovm_object_utils_begin"
2735 "`ovm_object_param_utils_begin"
2736 "`ovm_sequence_utils_begin"
2737 "`ovm_sequencer_utils_begin"
2739 "`ovm_component_utils_end"
2740 "`ovm_field_utils_end"
2741 "`ovm_object_utils_end"
2742 "`ovm_sequence_utils_end"
2743 "`ovm_sequencer_utils_end"
2745 "`uvm_component_utils_begin"
2746 "`uvm_component_param_utils_begin"
2747 "`uvm_field_utils_begin"
2748 "`uvm_object_utils_begin"
2749 "`uvm_object_param_utils_begin"
2750 "`uvm_sequence_utils_begin"
2751 "`uvm_sequencer_utils_begin"
2753 "`uvm_component_utils_end" ; Typo in spec, it's not uvm_component_end
2754 "`uvm_field_utils_end"
2755 "`uvm_object_utils_end"
2756 "`uvm_sequence_utils_end"
2757 "`uvm_sequencer_utils_end"
2759 "`vmm_data_member_begin"
2760 "`vmm_env_member_begin"
2761 "`vmm_scenario_member_begin"
2762 "`vmm_subenv_member_begin"
2763 "`vmm_xactor_member_begin"
2765 "`vmm_data_member_end"
2766 "`vmm_env_member_end"
2767 "`vmm_scenario_member_end"
2768 "`vmm_subenv_member_end"
2769 "`vmm_xactor_member_end"
2772 (defconst verilog-defun-level-not-generate-re
2774 (verilog-regexp-words
2775 `( "module" "macromodule" "primitive" "class" "program"
2776 "interface" "package" "config"))))
2778 (defconst verilog-defun-level-re
2780 (verilog-regexp-words
2782 `( "module" "macromodule" "primitive" "class" "program"
2783 "interface" "package" "config")
2784 `( "initial" "final" "always" "always_comb" "always_ff"
2785 "always_latch" "endtask" "endfunction" )))))
2787 (defconst verilog-defun-level-generate-only-re
2789 (verilog-regexp-words
2790 `( "initial" "final" "always" "always_comb" "always_ff"
2791 "always_latch" "endtask" "endfunction" ))))
2793 (defconst verilog-cpp-level-re
2795 (verilog-regexp-words
2797 "endmodule" "endprimitive" "endinterface" "endpackage" "endprogram" "endclass"
2800 (defconst verilog-dpi-import-export-re
2802 "\\(\\<\\(import\\|export\\)\\>\\s-+\"DPI\\(-C\\)?\"\\s-+\\(\\<\\(context\\|pure\\)\\>\\s-+\\)?\\([A-Za-z_][A-Za-z0-9_]*\\s-*=\\s-*\\)?\\<\\(function\\|task\\)\\>\\)"
2805 (defconst verilog-disable-fork-re "\\(disable\\|wait\\)\\s-+fork\\>")
2806 (defconst verilog-extended-case-re "\\(\\(unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\)")
2807 (defconst verilog-extended-complete-re
2808 (concat "\\(\\(\\<extern\\s-+\\|\\<\\(\\<\\(pure\\|context\\)\\>\\s-+\\)?virtual\\s-+\\|\\<protected\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)\\)"
2809 "\\|\\(\\(\\<typedef\\>\\s-+\\)*\\(\\<struct\\>\\|\\<union\\>\\|\\<class\\>\\)\\)"
2810 "\\|\\(\\(\\<\\(import\\|export\\)\\>\\s-+\\)?\\(\"DPI\\(-C\\)?\"\\s-+\\)?\\(\\<\\(pure\\|context\\)\\>\\s-+\\)?\\([A-Za-z_][A-Za-z0-9_]*\\s-*=\\s-*\\)?\\(function\\>\\|task\\>\\)\\)"
2811 "\\|" verilog-extended-case-re ))
2812 (defconst verilog-basic-complete-re
2814 (verilog-regexp-words
2816 "always" "assign" "always_latch" "always_ff" "always_comb" "constraint"
2817 "import" "initial" "final" "module" "macromodule" "repeat" "randcase" "while"
2818 "if" "for" "forever" "foreach" "else" "parameter" "do" "localparam" "assert"
2820 (defconst verilog-complete-reg
2822 verilog-extended-complete-re "\\|\\(" verilog-basic-complete-re "\\)"))
2824 (defconst verilog-end-statement-re
2825 (concat "\\(" verilog-beg-block-re "\\)\\|\\("
2826 verilog-end-block-re "\\)"))
2828 (defconst verilog-endcase-re
2829 (concat verilog-extended-case-re "\\|"
2834 (defconst verilog-exclude-str-start "/* -----\\/----- EXCLUDED -----\\/-----"
2835 "String used to mark beginning of excluded text.")
2836 (defconst verilog-exclude-str-end " -----/\\----- EXCLUDED -----/\\----- */"
2837 "String used to mark end of excluded text.")
2838 (defconst verilog-preprocessor-re
2843 (verilog-regexp-words
2851 "`nounconnected_drive"
2853 "`unconnected_drive"
2856 ;; two words: i.e. `ifdef DEFINE
2857 "\\<\\(`elsif\\|`ifn?def\\|`undef\\|`default_nettype\\|`begin_keywords\\)\\>\\s-"
2859 ;; `line number "filename" level
2860 "\\<\\(`line\\)\\>\\s-+[0-9]+\\s-+\"[^\"]+\"\\s-+[012]"
2862 ;;`include "file" or `include <file>
2863 "\\<\\(`include\\)\\>\\s-+\\(?:\"[^\"]+\"\\|<[^>]+>\\)"
2865 ;; `pragma <stuff> (no mention in IEEE 1800-2012 that pragma can span multiple lines
2866 "\\<\\(`pragma\\)\\>\\s-+.+$"
2868 ;; `timescale time_unit / time_precision
2869 "\\<\\(`timescale\\)\\>\\s-+10\\{0,2\\}\\s-*[munpf]?s\\s-*\\/\\s-*10\\{0,2\\}\\s-*[munpf]?s"
2871 ;; `define and `if can span multiple lines if line ends in '\'. NOTE: `if is not IEEE 1800-2012
2872 ;; from http://www.emacswiki.org/emacs/MultilineRegexp
2873 (concat "\\<\\(`define\\|`if\\)\\>" ; directive
2875 "\\(?:.*?\\(?:\n.*\\)*?\\)" ; definition: to end of line, then maybe more lines (excludes any trailing \n)
2876 "\\(?:\n\\s-*\n\\|\\'\\)") ; blank line or EOF
2878 ;; `<macro>() : i.e. `uvm_info(a,b,c) or any other pre-defined macro
2879 ;; Since parameters inside the macro can have parentheses, and
2880 ;; the macro can span multiple lines, just look for the opening
2881 ;; parentheses and then continue to the end of the first
2883 (concat "\\<`\\w+\\>\\s-*("
2884 "\\(?:.*?\\(?:\n.*\\)*?\\)" ; definition: to end of line, then maybe more lines (excludes any trailing \n)
2885 "\\(?:\n\\s-*\n\\|\\'\\)") ; blank line or EOF
2889 (defconst verilog-keywords
2890 (append verilog-compiler-directives
2892 "after" "alias" "always" "always_comb" "always_ff" "always_latch" "and"
2893 "assert" "assign" "assume" "automatic" "before" "begin" "bind"
2894 "bins" "binsof" "bit" "break" "buf" "bufif0" "bufif1" "byte"
2895 "case" "casex" "casez" "cell" "chandle" "class" "clocking" "cmos"
2896 "config" "const" "constraint" "context" "continue" "cover"
2897 "covergroup" "coverpoint" "cross" "deassign" "default" "defparam"
2898 "design" "disable" "dist" "do" "edge" "else" "end" "endcase"
2899 "endclass" "endclocking" "endconfig" "endfunction" "endgenerate"
2900 "endgroup" "endinterface" "endmodule" "endpackage" "endprimitive"
2901 "endprogram" "endproperty" "endspecify" "endsequence" "endtable"
2902 "endtask" "enum" "event" "expect" "export" "extends" "extern"
2903 "final" "first_match" "for" "force" "foreach" "forever" "fork"
2904 "forkjoin" "function" "generate" "genvar" "highz0" "highz1" "if"
2905 "iff" "ifnone" "ignore_bins" "illegal_bins" "import" "incdir"
2906 "include" "initial" "inout" "input" "inside" "instance" "int"
2907 "integer" "interface" "intersect" "join" "join_any" "join_none"
2908 "large" "liblist" "library" "local" "localparam" "logic"
2909 "longint" "macromodule" "mailbox" "matches" "medium" "modport" "module"
2910 "nand" "negedge" "new" "nmos" "nor" "noshowcancelled" "not"
2911 "notif0" "notif1" "null" "or" "output" "package" "packed"
2912 "parameter" "pmos" "posedge" "primitive" "priority" "program"
2913 "property" "protected" "pull0" "pull1" "pulldown" "pullup"
2914 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
2915 "randcase" "randsequence" "rcmos" "real" "realtime" "ref" "reg"
2916 "release" "repeat" "return" "rnmos" "rpmos" "rtran" "rtranif0"
2917 "rtranif1" "scalared" "semaphore" "sequence" "shortint" "shortreal"
2918 "showcancelled" "signed" "small" "solve" "specify" "specparam"
2919 "static" "string" "strong0" "strong1" "struct" "super" "supply0"
2920 "supply1" "table" "tagged" "task" "this" "throughout" "time"
2921 "timeprecision" "timeunit" "tran" "tranif0" "tranif1" "tri"
2922 "tri0" "tri1" "triand" "trior" "trireg" "type" "typedef" "union"
2923 "unique" "unsigned" "use" "uwire" "var" "vectored" "virtual" "void"
2924 "wait" "wait_order" "wand" "weak0" "weak1" "while" "wildcard"
2925 "wire" "with" "within" "wor" "xnor" "xor"
2927 "accept_on" "checker" "endchecker" "eventually" "global" "implies"
2928 "let" "nexttime" "reject_on" "restrict" "s_always" "s_eventually"
2929 "s_nexttime" "s_until" "s_until_with" "strong" "sync_accept_on"
2930 "sync_reject_on" "unique0" "until" "until_with" "untyped" "weak"
2932 "implements" "interconnect" "nettype" "soft"
2934 "List of Verilog keywords.")
2936 (defconst verilog-comment-start-regexp "//\\|/\\*"
2937 "Dual comment value for `comment-start-regexp'.")
2939 (defvar verilog-mode-syntax-table
2940 (let ((table (make-syntax-table)))
2941 ;; Populate the syntax TABLE.
2942 (modify-syntax-entry ?\\ "\\" table)
2943 (modify-syntax-entry ?+ "." table)
2944 (modify-syntax-entry ?- "." table)
2945 (modify-syntax-entry ?= "." table)
2946 (modify-syntax-entry ?% "." table)
2947 (modify-syntax-entry ?< "." table)
2948 (modify-syntax-entry ?> "." table)
2949 (modify-syntax-entry ?& "." table)
2950 (modify-syntax-entry ?| "." table)
2951 (modify-syntax-entry ?` "w" table) ; ` is part of definition symbols in Verilog
2952 (modify-syntax-entry ?_ "w" table)
2953 (modify-syntax-entry ?\' "." table)
2955 ;; Set up TABLE to handle block and line style comments.
2956 (if (featurep 'xemacs)
2958 ;; XEmacs (formerly Lucid) has the best implementation
2959 (modify-syntax-entry ?/ ". 1456" table)
2960 (modify-syntax-entry ?* ". 23" table)
2961 (modify-syntax-entry ?\n "> b" table))
2962 ;; Emacs does things differently, but we can work with it
2963 (modify-syntax-entry ?/ ". 124b" table)
2964 (modify-syntax-entry ?* ". 23" table)
2965 (modify-syntax-entry ?\n "> b" table))
2967 "Syntax table used in Verilog mode buffers.")
2969 (defvar verilog-font-lock-keywords nil
2970 "Default highlighting for Verilog mode.")
2972 (defvar verilog-font-lock-keywords-1 nil
2973 "Subdued level highlighting for Verilog mode.")
2975 (defvar verilog-font-lock-keywords-2 nil
2976 "Medium level highlighting for Verilog mode.
2977 See also `verilog-font-lock-extra-types'.")
2979 (defvar verilog-font-lock-keywords-3 nil
2980 "Gaudy level highlighting for Verilog mode.
2981 See also `verilog-font-lock-extra-types'.")
2983 (defvar verilog-font-lock-translate-off-face
2984 'verilog-font-lock-translate-off-face
2985 "Font to use for translated off regions.")
2986 (defface verilog-font-lock-translate-off-face
2989 (:background "gray90" :italic t ))
2992 (:background "gray10" :italic t ))
2993 (((class grayscale) (background light))
2994 (:foreground "DimGray" :italic t))
2995 (((class grayscale) (background dark))
2996 (:foreground "LightGray" :italic t))
2998 "Font lock mode face used to background highlight translate-off regions."
2999 :group 'font-lock-highlighting-faces)
3001 (defvar verilog-font-lock-p1800-face
3002 'verilog-font-lock-p1800-face
3003 "Font to use for p1800 keywords.")
3004 (defface verilog-font-lock-p1800-face
3007 (:foreground "DarkOrange3" :bold t ))
3010 (:foreground "orange1" :bold t ))
3012 "Font lock mode face used to highlight P1800 keywords."
3013 :group 'font-lock-highlighting-faces)
3015 (defvar verilog-font-lock-ams-face
3016 'verilog-font-lock-ams-face
3017 "Font to use for Analog/Mixed Signal keywords.")
3018 (defface verilog-font-lock-ams-face
3021 (:foreground "Purple" :bold t ))
3024 (:foreground "orange1" :bold t ))
3026 "Font lock mode face used to highlight AMS keywords."
3027 :group 'font-lock-highlighting-faces)
3029 (defvar verilog-font-grouping-keywords-face
3030 'verilog-font-lock-grouping-keywords-face
3031 "Font to use for Verilog Grouping Keywords (such as begin..end).")
3032 (defface verilog-font-lock-grouping-keywords-face
3035 (:foreground "Purple" :bold t ))
3038 (:foreground "orange1" :bold t ))
3040 "Font lock mode face used to highlight verilog grouping keywords."
3041 :group 'font-lock-highlighting-faces)
3043 (let* ((verilog-type-font-keywords
3047 "and" "bit" "buf" "bufif0" "bufif1" "cmos" "defparam"
3048 "event" "genvar" "inout" "input" "integer" "localparam"
3049 "logic" "mailbox" "nand" "nmos" "nor" "not" "notif0" "notif1" "or"
3050 "output" "parameter" "pmos" "pull0" "pull1" "pulldown" "pullup"
3051 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran"
3052 "rtranif0" "rtranif1" "semaphore" "signed" "struct" "supply"
3053 "supply0" "supply1" "time" "tran" "tranif0" "tranif1"
3054 "tri" "tri0" "tri1" "triand" "trior" "trireg" "typedef"
3055 "uwire" "vectored" "wand" "wire" "wor" "xnor" "xor"
3058 (verilog-pragma-keywords
3061 '("surefire" "auto" "synopsys" "rtl_synthesis" "verilint" "leda" "0in"
3064 (verilog-1800-2005-keywords
3067 '("alias" "assert" "assume" "automatic" "before" "bind"
3068 "bins" "binsof" "break" "byte" "cell" "chandle" "class"
3069 "clocking" "config" "const" "constraint" "context" "continue"
3070 "cover" "covergroup" "coverpoint" "cross" "deassign" "design"
3071 "dist" "do" "edge" "endclass" "endclocking" "endconfig"
3072 "endgroup" "endprogram" "endproperty" "endsequence" "enum"
3073 "expect" "export" "extends" "extern" "first_match" "foreach"
3074 "forkjoin" "genvar" "highz0" "highz1" "ifnone" "ignore_bins"
3075 "illegal_bins" "import" "incdir" "include" "inside" "instance"
3076 "int" "intersect" "large" "liblist" "library" "local" "longint"
3077 "matches" "medium" "modport" "new" "noshowcancelled" "null"
3078 "packed" "program" "property" "protected" "pull0" "pull1"
3079 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
3080 "randcase" "randsequence" "ref" "release" "return" "scalared"
3081 "sequence" "shortint" "shortreal" "showcancelled" "small" "solve"
3082 "specparam" "static" "string" "strong0" "strong1" "struct"
3083 "super" "tagged" "this" "throughout" "timeprecision" "timeunit"
3084 "type" "union" "unsigned" "use" "var" "virtual" "void"
3085 "wait_order" "weak0" "weak1" "wildcard" "with" "within"
3088 (verilog-1800-2009-keywords
3091 '("accept_on" "checker" "endchecker" "eventually" "global"
3092 "implies" "let" "nexttime" "reject_on" "restrict" "s_always"
3093 "s_eventually" "s_nexttime" "s_until" "s_until_with" "strong"
3094 "sync_accept_on" "sync_reject_on" "unique0" "until"
3095 "until_with" "untyped" "weak" ) nil )))
3097 (verilog-1800-2012-keywords
3100 '("implements" "interconnect" "nettype" "soft" ) nil )))
3102 (verilog-ams-keywords
3105 '("above" "abs" "absdelay" "acos" "acosh" "ac_stim"
3106 "aliasparam" "analog" "analysis" "asin" "asinh" "atan" "atan2" "atanh"
3107 "branch" "ceil" "connectmodule" "connectrules" "cos" "cosh" "ddt"
3108 "ddx" "discipline" "driver_update" "enddiscipline" "endconnectrules"
3109 "endnature" "endparamset" "exclude" "exp" "final_step" "flicker_noise"
3110 "floor" "flow" "from" "ground" "hypot" "idt" "idtmod" "inf"
3111 "initial_step" "laplace_nd" "laplace_np" "laplace_zd" "laplace_zp"
3112 "last_crossing" "limexp" "ln" "log" "max" "min" "nature"
3113 "net_resolution" "noise_table" "paramset" "potential" "pow" "sin"
3114 "sinh" "slew" "sqrt" "tan" "tanh" "timer" "transition" "white_noise"
3115 "wreal" "zi_nd" "zi_np" "zi_zd" ) nil )))
3117 (verilog-font-keywords
3121 "assign" "case" "casex" "casez" "randcase" "deassign"
3122 "default" "disable" "else" "endcase" "endfunction"
3123 "endgenerate" "endinterface" "endmodule" "endprimitive"
3124 "endspecify" "endtable" "endtask" "final" "for" "force" "return" "break"
3125 "continue" "forever" "fork" "function" "generate" "if" "iff" "initial"
3126 "interface" "join" "join_any" "join_none" "macromodule" "module" "negedge"
3127 "package" "endpackage" "always" "always_comb" "always_ff"
3128 "always_latch" "posedge" "primitive" "priority" "release"
3129 "repeat" "specify" "table" "task" "unique" "wait" "while"
3130 "class" "program" "endclass" "endprogram"
3133 (verilog-font-grouping-keywords
3136 '( "begin" "end" ) nil ))))
3138 (setq verilog-font-lock-keywords
3140 ;; Fontify all builtin keywords
3141 (concat "\\<\\(" verilog-font-keywords "\\|"
3142 ;; And user/system tasks and functions
3143 "\\$[a-zA-Z][a-zA-Z0-9_\\$]*"
3145 ;; Fontify all types
3146 (if verilog-highlight-grouping-keywords
3147 (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
3148 'verilog-font-lock-grouping-keywords-face)
3149 (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
3150 'font-lock-type-face))
3151 (cons (concat "\\<\\(" verilog-type-font-keywords "\\)\\>")
3152 'font-lock-type-face)
3153 ;; Fontify IEEE-1800-2005 keywords appropriately
3154 (if verilog-highlight-p1800-keywords
3155 (cons (concat "\\<\\(" verilog-1800-2005-keywords "\\)\\>")
3156 'verilog-font-lock-p1800-face)
3157 (cons (concat "\\<\\(" verilog-1800-2005-keywords "\\)\\>")
3158 'font-lock-type-face))
3159 ;; Fontify IEEE-1800-2009 keywords appropriately
3160 (if verilog-highlight-p1800-keywords
3161 (cons (concat "\\<\\(" verilog-1800-2009-keywords "\\)\\>")
3162 'verilog-font-lock-p1800-face)
3163 (cons (concat "\\<\\(" verilog-1800-2009-keywords "\\)\\>")
3164 'font-lock-type-face))
3165 ;; Fontify IEEE-1800-2012 keywords appropriately
3166 (if verilog-highlight-p1800-keywords
3167 (cons (concat "\\<\\(" verilog-1800-2012-keywords "\\)\\>")
3168 'verilog-font-lock-p1800-face)
3169 (cons (concat "\\<\\(" verilog-1800-2012-keywords "\\)\\>")
3170 'font-lock-type-face))
3171 ;; Fontify Verilog-AMS keywords
3172 (cons (concat "\\<\\(" verilog-ams-keywords "\\)\\>")
3173 'verilog-font-lock-ams-face)))
3175 (setq verilog-font-lock-keywords-1
3176 (append verilog-font-lock-keywords
3178 ;; Fontify module definitions
3180 "\\<\\(\\(macro\\)?module\\|primitive\\|class\\|program\\|interface\\|package\\|task\\)\\>\\s-*\\(\\sw+\\)"
3181 '(1 font-lock-keyword-face)
3182 '(3 font-lock-function-name-face 'prepend))
3183 ;; Fontify function definitions
3185 (concat "\\<function\\>\\s-+\\(integer\\|real\\(time\\)?\\|time\\)\\s-+\\(\\sw+\\)" )
3186 '(1 font-lock-keyword-face)
3187 '(3 font-lock-constant-face prepend))
3188 '("\\<function\\>\\s-+\\(\\[[^]]+\\]\\)\\s-+\\(\\sw+\\)"
3189 (1 font-lock-keyword-face)
3190 (2 font-lock-constant-face append))
3191 '("\\<function\\>\\s-+\\(\\sw+\\)"
3192 1 'font-lock-constant-face append))))
3194 (setq verilog-font-lock-keywords-2
3195 (append verilog-font-lock-keywords-1
3198 (concat "\\(//\\s-*\\(" verilog-pragma-keywords "\\)\\s-.*\\)")
3199 ;; Fontify escaped names
3200 '("\\(\\\\\\S-*\\s-\\)" 0 font-lock-function-name-face)
3201 ;; Fontify macro definitions/ uses
3202 '("`\\s-*[A-Za-z][A-Za-z0-9_]*" 0 (if (boundp 'font-lock-preprocessor-face)
3203 'font-lock-preprocessor-face
3204 'font-lock-type-face))
3205 ;; Fontify delays/numbers
3206 '("\\(@\\)\\|\\([ \t\n\f\r]#\\s-*\\(\\([0-9_.]+\\('s?[hdxbo][0-9a-fA-F_xz]*\\)?\\)\\|\\(([^()]+)\\|\\sw+\\)\\)\\)"
3207 0 font-lock-type-face append)
3208 ;; Fontify property/sequence cycle delays - these start with '##'
3209 '("\\(##\\(\\sw+\\|\\[[^]]+\\]\\)\\)"
3210 0 font-lock-type-face append)
3211 ;; Fontify instantiation names
3212 '("\\([A-Za-z][A-Za-z0-9_]*\\)\\s-*(" 1 font-lock-function-name-face)
3215 (setq verilog-font-lock-keywords-3
3216 (append verilog-font-lock-keywords-2
3217 (when verilog-highlight-translate-off
3219 ;; Fontify things in translate off regions
3220 '(verilog-match-translate-off
3221 (0 'verilog-font-lock-translate-off-face prepend))
3225 ;; Buffer state preservation
3227 (defmacro verilog-save-buffer-state (&rest body)
3228 "Execute BODY forms, saving state around insignificant change.
3229 Changes in text properties like `face' or `syntax-table' are
3230 considered insignificant. This macro allows text properties to
3231 be changed, even in a read-only buffer.
3233 A change is considered significant if it affects the buffer text
3234 in any way that isn't completely restored again. Any
3235 user-visible changes to the buffer must not be within a
3236 `verilog-save-buffer-state'."
3237 `(let ((inhibit-point-motion-hooks t)
3238 (verilog-no-change-functions t))
3239 ,(if (fboundp 'with-silent-modifications)
3240 `(with-silent-modifications ,@body)
3241 ;; Backward compatible version of with-silent-modifications
3242 `(let* ((modified (buffer-modified-p))
3243 (buffer-undo-list t)
3244 (inhibit-read-only t)
3245 (inhibit-modification-hooks t)
3246 ;; XEmacs ignores inhibit-modification-hooks.
3247 before-change-functions after-change-functions
3249 buffer-file-name ; Prevent primitives checking
3250 buffer-file-truename) ; for file modification
3255 (verilog-restore-buffer-modified-p nil)))))))
3258 (defvar verilog-save-font-mod-hooked nil
3259 "Local variable when inside a `verilog-save-font-no-change-functions' block.")
3260 (make-variable-buffer-local 'verilog-save-font-mod-hooked)
3262 (defmacro verilog-save-font-no-change-functions (&rest body)
3263 "Execute BODY forms, disabling all change hooks in BODY.
3264 Includes temporary disabling of `font-lock' to restore the buffer
3265 to full text form for parsing. Additional actions may be specified with
3266 `verilog-before-save-font-hook' and `verilog-after-save-font-hook'.
3267 For insignificant changes, see instead `verilog-save-buffer-state'."
3268 `(if verilog-save-font-mod-hooked ; Short-circuit a recursive call
3270 ;; Before version 20, match-string with font-lock returns a
3271 ;; vector that is not equal to the string. IE if on "input"
3272 ;; nil==(equal "input" (progn (looking-at "input") (match-string 0)))
3273 ;; Therefore we must remove and restore font-lock mode
3274 (verilog-run-hooks 'verilog-before-save-font-hook)
3275 (let* ((verilog-save-font-mod-hooked (- (point-max) (point-min)))
3276 ;; Significant speed savings with no font-lock properties
3277 (fontlocked (when (and (boundp 'font-lock-mode) font-lock-mode)
3280 (run-hook-with-args 'before-change-functions (point-min) (point-max))
3282 ;; Must inhibit and restore hooks before restoring font-lock
3283 (let* ((inhibit-point-motion-hooks t)
3284 (inhibit-modification-hooks t)
3285 (verilog-no-change-functions t)
3286 ;; XEmacs and pre-Emacs 21 ignore inhibit-modification-hooks.
3287 before-change-functions after-change-functions)
3290 (run-hook-with-args 'after-change-functions (point-min) (point-max)
3291 verilog-save-font-mod-hooked) ; old length
3292 (when fontlocked (font-lock-mode t))
3293 (verilog-run-hooks 'verilog-after-save-font-hook)))))
3296 ;; Comment detection and caching
3298 (defvar verilog-scan-cache-preserving nil
3299 "If true, the specified buffer's comment properties are static.
3300 Buffer changes will be ignored. See `verilog-inside-comment-or-string-p'
3301 and `verilog-scan'.")
3303 (defvar verilog-scan-cache-tick nil
3304 "Modification tick at which `verilog-scan' was last completed.")
3305 (make-variable-buffer-local 'verilog-scan-cache-tick)
3307 (defun verilog-scan-cache-flush ()
3308 "Flush the `verilog-scan' cache."
3309 (setq verilog-scan-cache-tick nil))
3311 (defun verilog-scan-cache-ok-p ()
3312 "Return t if the scan cache is up to date."
3313 (or (and verilog-scan-cache-preserving
3314 (eq verilog-scan-cache-preserving (current-buffer))
3315 verilog-scan-cache-tick)
3316 (equal verilog-scan-cache-tick (buffer-chars-modified-tick))))
3318 (defmacro verilog-save-scan-cache (&rest body)
3319 "Execute the BODY forms, allowing scan cache preservation within BODY.
3320 This requires that insertions must use `verilog-insert'."
3321 ;; If the buffer is out of date, trash it, as we'll not check later the tick
3322 ;; Note this must work properly if there's multiple layers of calls
3323 ;; to verilog-save-scan-cache even with differing ticks.
3325 (unless (verilog-scan-cache-ok-p) ; Must be before let
3326 (setq verilog-scan-cache-tick nil))
3327 (let* ((verilog-scan-cache-preserving (current-buffer)))
3330 (defun verilog-scan-region (beg end)
3331 "Parse between BEG and END for `verilog-inside-comment-or-string-p'.
3332 This creates v-cmts properties where comments are in force."
3333 ;; Why properties and not overlays? Overlays have much slower non O(1)
3335 ;; This function is warm - called on every verilog-insert
3338 (verilog-save-buffer-state
3341 (while (< (point) end)
3342 (cond ((looking-at "//")
3344 (or (search-forward "\n" end t)
3346 ;; "1+": The leading // or /* itself isn't considered as
3347 ;; being "inside" the comment, so that a (search-backward)
3348 ;; that lands at the start of the // won't mis-indicate
3349 ;; it's inside a comment. Also otherwise it would be
3350 ;; hard to find a commented out /*AS*/ vs one that isn't
3351 (put-text-property (1+ pt) (point) 'v-cmts t))
3352 ((looking-at "/\\*")
3354 (or (search-forward "*/" end t)
3355 ;; No error - let later code indicate it so we can
3356 ;; use inside functions on-the-fly
3357 ;;(error "%s: Unmatched /* */, at char %d"
3358 ;; (verilog-point-text) (point))
3360 (put-text-property (1+ pt) (point) 'v-cmts t))
3363 (or (re-search-forward "[^\\]\"" end t) ; don't forward-char first, since we look for a non backslash first
3364 ;; No error - let later code indicate it so we can
3366 (put-text-property (1+ pt) (point) 'v-cmts t))
3369 (if (re-search-forward "[/\"]" end t)
3371 (goto-char end))))))))))
3373 (defun verilog-scan ()
3374 "Parse the buffer, marking all comments with properties.
3375 Also assumes any text inserted since `verilog-scan-cache-tick'
3376 either is ok to parse as a non-comment, or `verilog-insert' was used."
3377 ;; See also `verilog-scan-debug' and `verilog-scan-and-debug'
3378 (unless (verilog-scan-cache-ok-p)
3380 (verilog-save-buffer-state
3382 (message "Scanning %s cache=%s cachetick=%S tick=%S" (current-buffer)
3383 verilog-scan-cache-preserving verilog-scan-cache-tick
3384 (buffer-chars-modified-tick)))
3385 (remove-text-properties (point-min) (point-max) '(v-cmts nil))
3386 (verilog-scan-region (point-min) (point-max))
3387 (setq verilog-scan-cache-tick (buffer-chars-modified-tick))
3388 (when verilog-debug (message "Scanning... done"))))))
3390 (defun verilog-scan-debug ()
3391 "For debugging, show with display face results of `verilog-scan'."
3393 ;;(if dbg (setq dbg (concat dbg (format "verilog-scan-debug\n"))))
3395 (goto-char (point-min))
3396 (remove-text-properties (point-min) (point-max) '(face nil))
3398 (cond ((get-text-property (point) 'v-cmts)
3399 (put-text-property (point) (1+ (point)) `face 'underline)
3400 ;;(if dbg (setq dbg (concat dbg (format " v-cmts at %S\n" (point)))))
3403 (goto-char (or (next-property-change (point)) (point-max))))))))
3405 (defun verilog-scan-and-debug ()
3406 "For debugging, run `verilog-scan' and `verilog-scan-debug'."
3407 (let (verilog-scan-cache-preserving
3408 verilog-scan-cache-tick)
3409 (goto-char (point-min))
3411 (verilog-scan-debug)))
3413 (defun verilog-inside-comment-or-string-p (&optional pos)
3414 "Check if optional point POS is inside a comment.
3415 This may require a slow pre-parse of the buffer with `verilog-scan'
3416 to establish comment properties on all text."
3417 ;; This function is very hot
3420 (and (>= pos (point-min))
3421 (get-text-property pos 'v-cmts))
3422 (get-text-property (point) 'v-cmts)))
3424 (defun verilog-insert (&rest stuff)
3425 "Insert STUFF arguments, tracking for `verilog-inside-comment-or-string-p'.
3426 Any insert that includes a comment must have the entire comment
3427 inserted using a single call to `verilog-insert'."
3430 (insert (car stuff))
3431 (setq stuff (cdr stuff)))
3432 (verilog-scan-region pt (point))))
3436 (defun verilog-declaration-end ()
3437 (search-forward ";"))
3439 (defun verilog-point-text (&optional pointnum)
3440 "Return text describing where POINTNUM or current point is (for errors).
3441 Use filename, if current buffer being edited shorten to just buffer name."
3442 (concat (or (and (equal (window-buffer) (current-buffer))
3446 ":" (int-to-string (1+ (count-lines (point-min) (or pointnum (point)))))))
3448 (defun electric-verilog-backward-sexp ()
3449 "Move backward over one balanced expression."
3451 ;; before that see if we are in a comment
3452 (verilog-backward-sexp))
3454 (defun electric-verilog-forward-sexp ()
3455 "Move forward over one balanced expression."
3457 ;; before that see if we are in a comment
3458 (verilog-forward-sexp))
3460 (defun verilog-forward-sexp-function (arg)
3461 "Move forward ARG sexps."
3462 ;; Used by hs-minor-mode
3464 (verilog-backward-sexp)
3465 (verilog-forward-sexp)))
3467 (defun verilog-backward-sexp ()
3472 (if (not (looking-at "\\<"))
3475 ((verilog-skip-backward-comment-or-string))
3476 ((looking-at "\\<else\\>")
3478 verilog-end-block-re
3479 "\\|\\(\\<else\\>\\)"
3480 "\\|\\(\\<if\\>\\)"))
3481 (while (and (not found)
3482 (verilog-re-search-backward reg nil 'move))
3484 ((match-end 1) ; matched verilog-end-block-re
3485 ;; try to leap back to matching outward block by striding across
3486 ;; indent level changing tokens then immediately
3487 ;; previous line governs indentation.
3488 (verilog-leap-to-head))
3489 ((match-end 2) ; else, we're in deep
3490 (setq elsec (1+ elsec)))
3491 ((match-end 3) ; found it
3492 (setq elsec (1- elsec))
3494 ;; Now previous line describes syntax
3495 (setq found 't))))))
3496 ((looking-at verilog-end-block-re)
3497 (verilog-leap-to-head))
3498 ((looking-at "\\(endmodule\\>\\)\\|\\(\\<endprimitive\\>\\)\\|\\(\\<endclass\\>\\)\\|\\(\\<endprogram\\>\\)\\|\\(\\<endinterface\\>\\)\\|\\(\\<endpackage\\>\\)")
3501 (verilog-re-search-backward "\\<\\(macro\\)?module\\>" nil 'move))
3503 (verilog-re-search-backward "\\<primitive\\>" nil 'move))
3505 (verilog-re-search-backward "\\<class\\>" nil 'move))
3507 (verilog-re-search-backward "\\<program\\>" nil 'move))
3509 (verilog-re-search-backward "\\<interface\\>" nil 'move))
3511 (verilog-re-search-backward "\\<package\\>" nil 'move))
3514 (backward-sexp 1))))
3519 (defun verilog-forward-sexp ()
3524 (if (not (looking-at "\\<"))
3527 ((verilog-skip-forward-comment-or-string)
3528 (verilog-forward-syntactic-ws))
3529 ((looking-at verilog-beg-block-re-ordered)
3532 ;; Search forward for matching end
3533 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
3535 ;; Search forward for matching endcase
3536 (setq reg "\\(\\<randcase\\>\\|\\(\\<unique0?\\>\\s-+\\|\\<priority\\>\\s-+\\)?\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )
3537 (setq md 3) ; ender is third item in regexp
3540 ;; might be "disable fork" or "wait fork"
3544 (looking-at verilog-disable-fork-re)
3545 (and (looking-at "fork")
3547 (setq here (point)) ; sometimes a fork is just a fork
3549 (looking-at verilog-disable-fork-re))))
3550 (progn ; it is a disable fork; ignore it
3551 (goto-char (match-end 0))
3554 (progn ; it is a nice simple fork
3555 (goto-char here) ; return from looking for "disable fork"
3556 ;; Search forward for matching join
3557 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))))
3559 ;; Search forward for matching endclass
3560 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
3563 ;; Search forward for matching endtable
3564 (setq reg "\\<endtable\\>" )
3567 ;; Search forward for matching endspecify
3568 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
3570 ;; Search forward for matching endfunction
3571 (setq reg "\\<endfunction\\>" )
3574 ;; Search forward for matching endfunction
3575 (setq reg "\\<endfunction\\>" )
3578 ;; Search forward for matching endtask
3579 (setq reg "\\<endtask\\>" )
3582 ;; Search forward for matching endtask
3583 (setq reg "\\<endtask\\>" )
3586 ;; Search forward for matching endgenerate
3587 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
3589 ;; Search forward for matching endgroup
3590 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
3592 ;; Search forward for matching endproperty
3593 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
3595 ;; Search forward for matching endsequence
3596 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" )
3597 (setq md 3)) ; 3 to get to endsequence in the reg above
3599 ;; Search forward for matching endclocking
3600 (setq reg "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)" )))
3607 (while (verilog-re-search-forward reg nil 'move)
3609 ((match-end md) ; a closer in regular expression, so we are climbing out
3610 (setq depth (1- depth))
3611 (if (= 0 depth) ; we are out!
3613 ((match-end 1) ; an opener in the r-e, so we are in deeper now
3614 (setq here (point)) ; remember where we started
3615 (goto-char (match-beginning 1))
3618 (looking-at verilog-disable-fork-re)
3619 (and (looking-at "fork")
3622 (looking-at verilog-disable-fork-re))))
3623 (progn ; it is a disable fork; another false alarm
3624 (goto-char (match-end 0)))
3625 (progn ; it is a simple fork (or has nothing to do with fork)
3627 (setq depth (1+ depth))))))))))
3628 (if (verilog-re-search-forward reg nil 'move)
3629 (throw 'skip 1))))))
3631 ((looking-at (concat
3632 "\\(\\<\\(macro\\)?module\\>\\)\\|"
3633 "\\(\\<primitive\\>\\)\\|"
3634 "\\(\\<class\\>\\)\\|"
3635 "\\(\\<program\\>\\)\\|"
3636 "\\(\\<interface\\>\\)\\|"
3637 "\\(\\<package\\>\\)"))
3640 (verilog-re-search-forward "\\<endmodule\\>" nil 'move))
3642 (verilog-re-search-forward "\\<endprimitive\\>" nil 'move))
3644 (verilog-re-search-forward "\\<endclass\\>" nil 'move))
3646 (verilog-re-search-forward "\\<endprogram\\>" nil 'move))
3648 (verilog-re-search-forward "\\<endinterface\\>" nil 'move))
3650 (verilog-re-search-forward "\\<endpackage\\>" nil 'move))
3653 (if (= (following-char) ?\) )
3655 (forward-sexp 1)))))
3658 (if (= (following-char) ?\) )
3660 (forward-sexp 1))))))
3662 (defun verilog-declaration-beg ()
3663 (verilog-re-search-backward verilog-declaration-re (bobp) t))
3669 (defvar verilog-which-tool 1)
3671 (define-derived-mode verilog-mode prog-mode "Verilog"
3672 "Major mode for editing Verilog code.
3673 \\<verilog-mode-map>
3674 See \\[describe-function] verilog-auto (\\[verilog-auto]) for details on how
3675 AUTOs can improve coding efficiency.
3677 Use \\[verilog-faq] for a pointer to frequently asked questions.
3679 NEWLINE, TAB indents for Verilog code.
3680 Delete converts tabs to spaces as it moves back.
3682 Supports highlighting.
3684 Turning on Verilog mode calls the value of the variable `verilog-mode-hook'
3685 with no args, if that value is non-nil.
3687 Variables controlling indentation/edit style:
3689 variable `verilog-indent-level' (default 3)
3690 Indentation of Verilog statements with respect to containing block.
3691 `verilog-indent-level-module' (default 3)
3692 Absolute indentation of Module level Verilog statements.
3693 Set to 0 to get initial and always statements lined up
3694 on the left side of your screen.
3695 `verilog-indent-level-declaration' (default 3)
3696 Indentation of declarations with respect to containing block.
3697 Set to 0 to get them list right under containing block.
3698 `verilog-indent-level-behavioral' (default 3)
3699 Indentation of first begin in a task or function block
3700 Set to 0 to get such code to lined up underneath the task or
3702 `verilog-indent-level-directive' (default 1)
3703 Indentation of \\=`ifdef/\\=`endif blocks.
3704 `verilog-cexp-indent' (default 1)
3705 Indentation of Verilog statements broken across lines i.e.:
3708 `verilog-case-indent' (default 2)
3709 Indentation for case statements.
3710 `verilog-auto-newline' (default nil)
3711 Non-nil means automatically newline after semicolons and the punctuation
3713 `verilog-auto-indent-on-newline' (default t)
3714 Non-nil means automatically indent line after newline.
3715 `verilog-tab-always-indent' (default t)
3716 Non-nil means TAB in Verilog mode should always reindent the current line,
3717 regardless of where in the line point is when the TAB command is used.
3718 `verilog-indent-begin-after-if' (default t)
3719 Non-nil means to indent begin statements following a preceding
3720 if, else, while, for and repeat statements, if any. Otherwise,
3721 the begin is lined up with the preceding token. If t, you get:
3723 begin // amount of indent based on `verilog-cexp-indent'
3727 `verilog-auto-endcomments' (default t)
3728 Non-nil means a comment /* ... */ is set after the ends which ends
3729 cases, tasks, functions and modules.
3730 The type and name of the object will be set between the braces.
3731 `verilog-minimum-comment-distance' (default 10)
3732 Minimum distance (in lines) between begin and end required before a comment
3733 will be inserted. Setting this variable to zero results in every
3734 end acquiring a comment; the default avoids too many redundant
3735 comments in tight quarters.
3736 `verilog-auto-lineup' (default `declarations')
3737 List of contexts where auto lineup of code should be done.
3739 Variables controlling other actions:
3741 `verilog-linter' (default `surelint')
3742 Unix program to call to run the lint checker. This is the default
3743 command for \\[compile-command] and \\[verilog-auto-save-compile].
3745 See \\[customize] for the complete list of variables.
3747 AUTO expansion functions are, in part:
3749 \\[verilog-auto] Expand AUTO statements.
3750 \\[verilog-delete-auto] Remove the AUTOs.
3751 \\[verilog-inject-auto] Insert AUTOs for the first time.
3753 Some other functions are:
3755 \\[verilog-complete-word] Complete word with appropriate possibilities.
3756 \\[verilog-mark-defun] Mark function.
3757 \\[verilog-beg-of-defun] Move to beginning of current function.
3758 \\[verilog-end-of-defun] Move to end of current function.
3759 \\[verilog-label-be] Label matching begin ... end, fork ... join, etc statements.
3761 \\[verilog-comment-region] Put marked area in a comment.
3762 \\[verilog-uncomment-region] Uncomment an area commented with \\[verilog-comment-region].
3763 \\[verilog-insert-block] Insert begin ... end.
3764 \\[verilog-star-comment] Insert /* ... */.
3766 \\[verilog-sk-always] Insert an always @(AS) begin .. end block.
3767 \\[verilog-sk-begin] Insert a begin .. end block.
3768 \\[verilog-sk-case] Insert a case block, prompting for details.
3769 \\[verilog-sk-for] Insert a for (...) begin .. end block, prompting for details.
3770 \\[verilog-sk-generate] Insert a generate .. endgenerate block.
3771 \\[verilog-sk-header] Insert a header block at the top of file.
3772 \\[verilog-sk-initial] Insert an initial begin .. end block.
3773 \\[verilog-sk-fork] Insert a fork begin .. end .. join block.
3774 \\[verilog-sk-module] Insert a module .. (/*AUTOARG*/);.. endmodule block.
3775 \\[verilog-sk-ovm-class] Insert an OVM Class block.
3776 \\[verilog-sk-uvm-object] Insert an UVM Object block.
3777 \\[verilog-sk-uvm-component] Insert an UVM Component block.
3778 \\[verilog-sk-primitive] Insert a primitive .. (.. );.. endprimitive block.
3779 \\[verilog-sk-repeat] Insert a repeat (..) begin .. end block.
3780 \\[verilog-sk-specify] Insert a specify .. endspecify block.
3781 \\[verilog-sk-task] Insert a task .. begin .. end endtask block.
3782 \\[verilog-sk-while] Insert a while (...) begin .. end block, prompting for details.
3783 \\[verilog-sk-casex] Insert a casex (...) item: begin.. end endcase block, prompting for details.
3784 \\[verilog-sk-casez] Insert a casez (...) item: begin.. end endcase block, prompting for details.
3785 \\[verilog-sk-if] Insert an if (..) begin .. end block.
3786 \\[verilog-sk-else-if] Insert an else if (..) begin .. end block.
3787 \\[verilog-sk-comment] Insert a comment block.
3788 \\[verilog-sk-assign] Insert an assign .. = ..; statement.
3789 \\[verilog-sk-function] Insert a function .. begin .. end endfunction block.
3790 \\[verilog-sk-input] Insert an input declaration, prompting for details.
3791 \\[verilog-sk-output] Insert an output declaration, prompting for details.
3792 \\[verilog-sk-state-machine] Insert a state machine definition, prompting for details.
3793 \\[verilog-sk-inout] Insert an inout declaration, prompting for details.
3794 \\[verilog-sk-wire] Insert a wire declaration, prompting for details.
3795 \\[verilog-sk-reg] Insert a register declaration, prompting for details.
3796 \\[verilog-sk-define-signal] Define signal under point as a register at the top of the module.
3798 All key bindings can be seen in a Verilog-buffer with \\[describe-bindings].
3799 Key bindings specific to `verilog-mode-map' are:
3801 \\{verilog-mode-map}"
3802 :abbrev-table verilog-mode-abbrev-table
3803 (set (make-local-variable 'beginning-of-defun-function)
3804 'verilog-beg-of-defun)
3805 (set (make-local-variable 'end-of-defun-function)
3806 'verilog-end-of-defun)
3807 (set-syntax-table verilog-mode-syntax-table)
3808 (set (make-local-variable 'indent-line-function)
3809 #'verilog-indent-line-relative)
3810 (set (make-local-variable 'comment-indent-function) 'verilog-comment-indent)
3811 (set (make-local-variable 'parse-sexp-ignore-comments) nil)
3812 (set (make-local-variable 'comment-start) "// ")
3813 (set (make-local-variable 'comment-end) "")
3814 (set (make-local-variable 'comment-start-skip) "/\\*+ *\\|// *")
3815 (set (make-local-variable 'comment-multi-line) nil)
3816 ;; Set up for compilation
3817 (setq verilog-which-tool 1)
3818 (setq verilog-tool 'verilog-linter)
3819 (verilog-set-compile-command)
3820 (when (boundp 'hack-local-variables-hook) ; Also modify any file-local-variables
3821 (add-hook 'hack-local-variables-hook 'verilog-modify-compile-command t))
3824 (when (featurep 'xemacs)
3825 (easy-menu-add verilog-stmt-menu)
3826 (easy-menu-add verilog-menu)
3827 (setq mode-popup-menu (cons "Verilog Mode" verilog-stmt-menu)))
3829 ;; Stuff for GNU Emacs
3830 (set (make-local-variable 'font-lock-defaults)
3831 `((verilog-font-lock-keywords
3832 verilog-font-lock-keywords-1
3833 verilog-font-lock-keywords-2
3834 verilog-font-lock-keywords-3)
3836 ,(if (functionp 'syntax-ppss)
3837 ;; verilog-beg-of-defun uses syntax-ppss, and syntax-ppss uses
3838 ;; font-lock-beginning-of-syntax-function, so
3839 ;; font-lock-beginning-of-syntax-function, can't use
3840 ;; verilog-beg-of-defun.
3842 'verilog-beg-of-defun)))
3843 ;;------------------------------------------------------------
3844 ;; now hook in 'verilog-highlight-include-files (eldo-mode.el&spice-mode.el)
3845 ;; all buffer local:
3846 (unless noninteractive ; Else can't see the result, and change hooks are slow
3847 (when (featurep 'xemacs)
3848 (make-local-hook 'font-lock-mode-hook)
3849 (make-local-hook 'font-lock-after-fontify-buffer-hook); doesn't exist in Emacs
3850 (make-local-hook 'after-change-functions))
3851 (add-hook 'font-lock-mode-hook 'verilog-highlight-buffer t t)
3852 (add-hook 'font-lock-after-fontify-buffer-hook 'verilog-highlight-buffer t t) ; not in Emacs
3853 (add-hook 'after-change-functions 'verilog-highlight-region t t))
3855 ;; Tell imenu how to handle Verilog.
3856 (set (make-local-variable 'imenu-generic-expression)
3857 verilog-imenu-generic-expression)
3858 ;; Tell which-func-modes that imenu knows about verilog
3859 (when (and (boundp 'which-func-modes) (listp which-func-modes))
3860 (add-to-list 'which-func-modes 'verilog-mode))
3862 (when (boundp 'hs-special-modes-alist)
3863 (unless (assq 'verilog-mode hs-special-modes-alist)
3864 (setq hs-special-modes-alist
3865 (cons '(verilog-mode-mode "\\<begin\\>" "\\<end\\>" nil
3866 verilog-forward-sexp-function)
3867 hs-special-modes-alist))))
3870 (add-hook 'write-contents-hooks 'verilog-auto-save-check nil 'local)
3871 ;; verilog-mode-hook call added by define-derived-mode
3874 ;;; Electric functions:
3877 (defun electric-verilog-terminate-line (&optional arg)
3878 "Terminate line and indent next line.
3879 With optional ARG, remove existing end of line comments."
3881 ;; before that see if we are in a comment
3882 (let ((state (save-excursion (verilog-syntax-ppss))))
3884 ((nth 7 state) ; Inside // comment
3887 (delete-horizontal-space)
3892 (beginning-of-line)))
3893 (verilog-indent-line))
3894 ((nth 4 state) ; Inside any comment (hence /**/)
3896 (verilog-more-comment))
3898 ;; First, check if current line should be indented
3900 (delete-horizontal-space)
3902 (skip-chars-forward " \t")
3903 (if (looking-at verilog-auto-end-comment-lines-re)
3904 (let ((indent-str (verilog-indent-line)))
3905 ;; Maybe we should set some endcomments
3906 (if verilog-auto-endcomments
3907 (verilog-set-auto-endcomments indent-str arg))
3909 (delete-horizontal-space)
3916 (delete-horizontal-space)
3918 ;; see if we should line up assignments
3920 (if (or (eq 'all verilog-auto-lineup)
3921 (eq 'assignments verilog-auto-lineup))
3922 (verilog-pretty-expr t "\\(<\\|:\\)?=" ))
3926 (if verilog-auto-indent-on-newline
3927 (verilog-indent-line)))
3931 (defun electric-verilog-terminate-and-indent ()
3932 "Insert a newline and indent for the next statement."
3934 (electric-verilog-terminate-line 1))
3936 (defun electric-verilog-semi ()
3937 "Insert `;' character and reindent the line."
3939 (verilog-insert-last-command-event)
3941 (if (or (verilog-in-comment-or-string-p)
3942 (verilog-in-escaped-name-p))
3946 (verilog-forward-ws&directives)
3947 (verilog-indent-line))
3948 (if (and verilog-auto-newline
3949 (not (verilog-parenthesis-depth)))
3950 (electric-verilog-terminate-line))))
3952 (defun electric-verilog-semi-with-comment ()
3953 "Insert `;' character, reindent the line and indent for comment."
3958 (verilog-indent-line))
3959 (indent-for-comment))
3961 (defun electric-verilog-colon ()
3962 "Insert `:' and do all indentations except line indent on this line."
3964 (verilog-insert-last-command-event)
3965 ;; Do nothing if within string.
3967 (verilog-within-string)
3968 (not (verilog-in-case-region-p)))
3972 (lim (progn (verilog-beg-of-statement) (point))))
3974 (verilog-backward-case-item lim)
3975 (verilog-indent-line)))
3976 ;; (let ((verilog-tab-always-indent nil))
3977 ;; (verilog-indent-line))
3980 ;;(defun electric-verilog-equal ()
3981 ;; "Insert `=', and do indentation if within block."
3983 ;; (verilog-insert-last-command-event)
3984 ;; Could auto line up expressions, but not yet
3985 ;; (if (eq (car (verilog-calculate-indent)) 'block)
3986 ;; (let ((verilog-tab-always-indent nil))
3987 ;; (verilog-indent-command)))
3990 (defun electric-verilog-tick ()
3991 "Insert back-tick, and indent to column 0 if this is a CPP directive."
3993 (verilog-insert-last-command-event)
3995 (if (verilog-in-directive-p)
3996 (verilog-indent-line))))
3998 (defun electric-verilog-tab ()
3999 "Function called when TAB is pressed in Verilog mode."
4001 ;; If verilog-tab-always-indent, indent the beginning of the line.
4003 ;; The region is active, indent it.
4004 ((and (region-active-p)
4005 (not (eq (region-beginning) (region-end))))
4006 (indent-region (region-beginning) (region-end) nil))
4007 ((or verilog-tab-always-indent
4009 (skip-chars-backward " \t")
4011 (let* ((oldpnt (point))
4015 (skip-chars-forward " \t")
4016 (verilog-indent-line)
4017 (back-to-indentation)
4019 (if (< (point) boi-point)
4020 (back-to-indentation)
4021 (cond ((not verilog-tab-to-comment))
4025 (indent-for-comment)
4026 (when (and (eolp) (= oldpnt (point)))
4027 ;; kill existing comment
4029 (re-search-forward comment-start-skip oldpnt 'move)
4030 (goto-char (match-beginning 0))
4031 (skip-chars-backward " \t")
4032 (kill-region (point) oldpnt)))))))
4033 (t (progn (insert "\t")))))
4036 ;;; Interactive functions:
4039 (defun verilog-indent-buffer ()
4040 "Indent-region the entire buffer as Verilog code.
4041 To call this from the command line, see \\[verilog-batch-indent]."
4044 (indent-region (point-min) (point-max) nil))
4046 (defun verilog-insert-block ()
4047 "Insert Verilog begin ... end; block in the code with right indentation."
4049 (verilog-indent-line)
4051 (electric-verilog-terminate-line)
4053 (electric-verilog-terminate-line)
4056 (verilog-indent-line)))
4058 (defun verilog-star-comment ()
4059 "Insert Verilog star comment at point."
4061 (verilog-indent-line)
4069 (defun verilog-insert-1 (fmt max)
4070 "Use format string FMT to insert integers 0 to MAX - 1.
4071 Inserts one integer per line, at the current column. Stops early
4072 if it reaches the end of the buffer."
4073 (let ((col (current-column))
4077 (insert (format fmt n))
4079 ;; Note that this function does not bother to check for lines
4080 ;; shorter than col.
4084 (move-to-column col))))))
4086 (defun verilog-insert-indices (max)
4087 "Insert a set of indices into a rectangle.
4088 The upper left corner is defined by point. Indices begin with 0
4089 and extend to the MAX - 1. If no prefix arg is given, the user
4090 is prompted for a value. The indices are surrounded by square
4091 brackets []. For example, the following code with the point
4092 located after the first `a' gives:
4098 a = b ==> insert-indices ==> a[ 4] = b
4104 (interactive "NMAX: ")
4105 (verilog-insert-1 "[%3d]" max))
4107 (defun verilog-generate-numbers (max)
4108 "Insert a set of generated numbers into a rectangle.
4109 The upper left corner is defined by point. The numbers are padded to three
4110 digits, starting with 000 and extending to (MAX - 1). If no prefix argument
4111 is supplied, then the user is prompted for the MAX number. Consider the
4112 following code fragment:
4118 buf buf ==> generate-numbers ==> buf buf004
4124 (interactive "NMAX: ")
4125 (verilog-insert-1 "%3.3d" max))
4127 (defun verilog-mark-defun ()
4128 "Mark the current Verilog function (or procedure).
4129 This puts the mark at the end, and point at the beginning."
4131 (if (featurep 'xemacs)
4134 (verilog-end-of-defun)
4136 (verilog-beg-of-defun)
4137 (if (fboundp 'zmacs-activate-region)
4138 (zmacs-activate-region)))
4141 (defun verilog-comment-region (start end)
4142 ;; checkdoc-params: (start end)
4143 "Put the region into a Verilog comment.
4144 The comments that are in this area are \"deformed\":
4145 `*)' becomes `!(*' and `}' becomes `!{'.
4146 These deformed comments are returned to normal if you use
4147 \\[verilog-uncomment-region] to undo the commenting.
4149 The commented area starts with `verilog-exclude-str-start', and ends with
4150 `verilog-exclude-str-end'. But if you change these variables,
4151 \\[verilog-uncomment-region] won't recognize the comments."
4154 ;; Insert start and endcomments
4156 (if (and (save-excursion (skip-chars-forward " \t") (eolp))
4157 (not (save-excursion (skip-chars-backward " \t") (bolp))))
4159 (beginning-of-line))
4160 (insert verilog-exclude-str-end)
4165 (insert verilog-exclude-str-start)
4167 ;; Replace end-comments within commented area
4170 (while (re-search-backward "\\*/" start t)
4171 (replace-match "*-/" t t)))
4173 (let ((s+1 (1+ start)))
4174 (while (re-search-backward "/\\*" s+1 t)
4175 (replace-match "/-*" t t))))))
4177 (defun verilog-uncomment-region ()
4178 "Uncomment a commented area; change deformed comments back to normal.
4179 This command does nothing if the pointer is not in a commented
4180 area. See also `verilog-comment-region'."
4183 (let ((start (point))
4185 ;; Find the boundaries of the comment
4187 (setq start (progn (search-backward verilog-exclude-str-start nil t)
4189 (setq end (progn (search-forward verilog-exclude-str-end nil t)
4191 ;; Check if we're really inside a comment
4192 (if (or (equal start (point)) (<= end (point)))
4193 (message "Not standing within commented area.")
4195 ;; Remove endcomment
4198 (let ((pos (point)))
4200 (delete-region pos (1+ (point))))
4201 ;; Change comments back to normal
4203 (while (re-search-backward "\\*-/" start t)
4204 (replace-match "*/" t t)))
4206 (while (re-search-backward "/-\\*" start t)
4207 (replace-match "/*" t t)))
4208 ;; Remove start comment
4211 (let ((pos (point)))
4213 (delete-region pos (1+ (point)))))))))
4215 (defun verilog-beg-of-defun ()
4216 "Move backward to the beginning of the current function or procedure."
4218 (verilog-re-search-backward verilog-defun-re nil 'move))
4220 (defun verilog-beg-of-defun-quick ()
4221 "Move backward to the beginning of the current function or procedure.
4222 Uses `verilog-scan' cache."
4224 (verilog-re-search-backward-quick verilog-defun-re nil 'move))
4226 (defun verilog-end-of-defun ()
4227 "Move forward to the end of the current function or procedure."
4229 (verilog-re-search-forward verilog-end-defun-re nil 'move))
4231 (defun verilog-get-end-of-defun ()
4233 (cond ((verilog-re-search-forward-quick verilog-end-defun-re nil t)
4236 (error "%s: Can't find endmodule" (verilog-point-text))
4239 (defun verilog-label-be ()
4240 "Label matching begin ... end, fork ... join and case ... endcase statements."
4243 (case-fold-search nil)
4246 (verilog-beg-of-defun)
4249 (verilog-end-of-defun)
4251 (goto-char (marker-position b))
4253 (message "Relabeling module..."))
4255 (> (marker-position e) (point))
4256 (verilog-re-search-forward
4257 verilog-auto-end-comment-lines-re
4259 (goto-char (match-beginning 0))
4260 (let ((indent-str (verilog-indent-line)))
4261 (verilog-set-auto-endcomments indent-str 't)
4263 (delete-horizontal-space))
4265 (if (= 9 (% cnt 10))
4266 (message "%d..." cnt)))
4271 (message "%d lines auto commented" cnt))))
4273 (defun verilog-beg-of-statement ()
4274 "Move backward to beginning of statement."
4276 ;; Move back token by token until we see the end
4277 ;; of some earlier line.
4280 ;; If the current point does not begin a new
4281 ;; statement, as in the character ahead of us is a ';', or SOF
4282 ;; or the string after us unambiguously starts a statement,
4283 ;; or the token before us unambiguously ends a statement,
4284 ;; then move back a token and test again.
4286 ;; stop if beginning of buffer
4288 ;; stop if looking at a pre-processor directive
4289 (looking-at "`\\w+")
4290 ;; stop if we find a ;
4291 (= (preceding-char) ?\;)
4292 ;; stop if we see a named coverpoint
4293 (looking-at "\\w+\\W*:\\W*\\(coverpoint\\|cross\\|constraint\\)")
4294 ;; keep going if we are in the middle of a word
4295 (not (or (looking-at "\\<") (forward-word -1)))
4296 ;; stop if we see an assertion (perhaps labeled)
4298 (looking-at "\\(\\w+\\W*:\\W*\\)?\\(\\<\\(assert\\|assume\\|cover\\)\\>\\s-+\\<property\\>\\)\\|\\(\\<assert\\>\\)")
4302 (verilog-backward-token)
4303 (if (and (looking-at verilog-label-re)
4304 (not (looking-at verilog-end-block-re)))
4307 ;; stop if we see an extended complete reg, perhaps a complete one
4309 (looking-at verilog-complete-reg)
4311 (while (and (looking-at verilog-extended-complete-re)
4312 (progn (setq p (point))
4313 (verilog-backward-token)
4316 ;; stop if we see a complete reg (previous found extended ones)
4317 (looking-at verilog-basic-complete-re)
4318 ;; stop if previous token is an ender
4320 (verilog-backward-token)
4321 (looking-at verilog-end-block-re))))
4322 (verilog-backward-syntactic-ws)
4323 (verilog-backward-token))
4324 ;; Now point is where the previous line ended.
4325 (verilog-forward-syntactic-ws)
4326 ;; Skip forward over any preprocessor directives, as they have wacky indentation
4327 (if (looking-at verilog-preprocessor-re)
4328 (progn (goto-char (match-end 0))
4329 (verilog-forward-syntactic-ws)))))
4331 (defun verilog-beg-of-statement-1 ()
4332 "Move backward to beginning of statement."
4334 (if (verilog-in-comment-p)
4335 (verilog-backward-syntactic-ws))
4338 (while (not (looking-at verilog-complete-reg))
4340 (verilog-backward-syntactic-ws)
4342 (= (preceding-char) ?\;)
4344 (verilog-backward-token)
4345 (looking-at verilog-ends-re)))
4349 (verilog-forward-syntactic-ws)))
4352 ;; (not (looking-at verilog-complete-reg))
4354 ;; (not (= (preceding-char) ?\;)))
4355 ;; (verilog-backward-token)
4356 ;; (verilog-backward-syntactic-ws)
4357 ;; (setq pt (point)))
4359 ;; ;(verilog-forward-syntactic-ws)
4361 (defun verilog-end-of-statement ()
4362 "Move forward to end of current statement."
4366 ((verilog-in-directive-p)
4370 ((looking-at verilog-beg-block-re)
4371 (verilog-forward-sexp))
4373 ((equal (char-after) ?\})
4376 ;; Skip to end of statement
4377 ((condition-case nil
4382 (verilog-skip-forward-comment-or-string)
4385 (cond ((looking-at "[ \t]*;")
4386 (skip-chars-forward "^;")
4388 (throw 'found (point)))
4391 (looking-at verilog-beg-block-re))
4392 (goto-char (match-beginning 0))
4394 ((looking-at "[ \t]*)")
4395 (throw 'found (point)))
4397 (throw 'found (point)))
4403 ;; Skip a whole block
4406 (verilog-re-search-forward verilog-end-statement-re nil 'move)
4407 (setq nest (if (match-end 1)
4411 (throw 'found (point)))
4413 (throw 'found (verilog-end-of-statement))))))
4416 (defun verilog-in-case-region-p ()
4417 "Return true if in a case region.
4418 More specifically, point @ in the line foo : @ begin"
4422 (progn (verilog-forward-syntactic-ws)
4423 (looking-at "\\<begin\\>"))
4424 (progn (verilog-backward-syntactic-ws)
4425 (= (preceding-char) ?\:)))
4429 (verilog-re-search-backward
4430 (concat "\\(\\<module\\>\\)\\|\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|"
4431 "\\(\\<endcase\\>\\)\\>")
4435 (setq nest (1+ nest)))
4439 (setq nest (1- nest)))
4441 (throw 'found (= nest 0)))))))
4444 (defun verilog-backward-up-list (arg)
4445 "Call `backward-up-list' ARG, ignoring comments."
4446 (let ((parse-sexp-ignore-comments t))
4447 (backward-up-list arg)))
4449 (defun verilog-forward-sexp-cmt (arg)
4450 "Call `forward-sexp' ARG, inside comments."
4451 (let ((parse-sexp-ignore-comments nil))
4452 (forward-sexp arg)))
4454 (defun verilog-forward-sexp-ign-cmt (arg)
4455 "Call `forward-sexp' ARG, ignoring comments."
4456 (let ((parse-sexp-ignore-comments t))
4457 (forward-sexp arg)))
4459 (defun verilog-in-generate-region-p ()
4460 "Return true if in a generate region.
4461 More specifically, after a generate and before an endgenerate."
4468 (verilog-re-search-backward
4469 "\\<\\(module\\)\\|\\(generate\\)\\|\\(endgenerate\\)\\>" nil 'move)
4471 ((match-end 1) ; module - we have crawled out
4473 ((match-end 2) ; generate
4474 (setq nest (1- nest)))
4475 ((match-end 3) ; endgenerate
4476 (setq nest (1+ nest))))))))
4477 (= nest 0) )) ; return nest
4479 (defun verilog-in-fork-region-p ()
4480 "Return true if between a fork and join."
4482 (let ((lim (save-excursion (verilog-beg-of-defun) (point)))
4487 (verilog-re-search-backward "\\<\\(fork\\)\\|\\(join\\(_any\\|_none\\)?\\)\\>" lim 'move)
4489 ((match-end 1) ; fork
4490 (setq nest (1- nest)))
4491 ((match-end 2) ; join
4492 (setq nest (1+ nest)))))))
4493 (= nest 0) )) ; return nest
4495 (defun verilog-in-deferred-immediate-final-p ()
4496 "Return true if inside an `assert/assume/cover final' statement."
4498 (and (looking-at "final")
4499 (verilog-looking-back "\\<\\(?:assert\\|assume\\|cover\\)\\>\\s-+" nil))
4502 (defun verilog-backward-case-item (lim)
4503 "Skip backward to nearest enclosing case item.
4504 Limit search to point LIM."
4510 (verilog-re-search-backward verilog-endcomment-reason-re
4513 ;; Try to find the real :
4514 (if (save-excursion (search-backward ":" lim1 t))
4520 (verilog-re-search-backward "\\(\\[\\)\\|\\(\\]\\)\\|\\(:\\)"
4524 (setq colon (1+ colon))
4526 (error "%s: unbalanced [" (verilog-point-text))))
4528 (setq colon (1- colon)))
4531 (setq colon (1+ colon)))))
4532 ;; Skip back to beginning of case item
4533 (skip-chars-backward "\t ")
4534 (verilog-skip-backward-comment-or-string)
4539 (verilog-re-search-backward
4540 "\\<\\(case[zx]?\\)\\>\\|;\\|\\<end\\>" nil 'move)
4544 (goto-char (match-end 1))
4545 (verilog-forward-ws&directives)
4546 (if (looking-at "(")
4549 (verilog-forward-ws&directives)))
4552 (goto-char (match-end 0))
4553 (verilog-forward-ws&directives)
4555 (error "Malformed case item"))))
4556 (setq str (buffer-substring b e))
4560 "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
4561 (setq str (concat (substring str 0 e) "...")))
4565 ;;; Other functions:
4568 (defun verilog-kill-existing-comment ()
4569 "Kill auto comment on this line."
4577 (search-forward "//" e t))))
4579 (delete-region (- b 2) e)))))
4581 (defconst verilog-directive-nest-re
4582 (concat "\\(`else\\>\\)\\|"
4583 "\\(`endif\\>\\)\\|"
4585 "\\(`ifdef\\>\\)\\|"
4586 "\\(`ifndef\\>\\)\\|"
4589 (defun verilog-set-auto-endcomments (indent-str kill-existing-comment)
4590 "Add ending comment with given INDENT-STR.
4591 With KILL-EXISTING-COMMENT, remove what was there before.
4592 Insert `// case: 7 ' or `// NAME ' on this line if appropriate.
4593 Insert `// case expr ' if this line ends a case block.
4594 Insert `// ifdef FOO ' if this line ends code conditional on FOO.
4595 Insert `// NAME ' if this line ends a function, task, module,
4596 primitive or interface named NAME."
4599 (; Comment close preprocessor directives
4601 (looking-at "\\(`endif\\)\\|\\(`else\\)")
4602 (or kill-existing-comment
4603 (not (save-excursion
4605 (search-backward "//" (point-at-bol) t)))))
4608 (else (if (match-end 2) "!" " ")))
4610 (if kill-existing-comment
4611 (verilog-kill-existing-comment))
4612 (delete-horizontal-space)
4615 (while (and (/= nest 0)
4616 (verilog-re-search-backward verilog-directive-nest-re nil 'move))
4618 ((match-end 1) ; `else
4621 ((match-end 2) ; `endif
4622 (setq nest (1+ nest)))
4623 ((match-end 3) ; `if
4624 (setq nest (1- nest)))
4625 ((match-end 4) ; `ifdef
4626 (setq nest (1- nest)))
4627 ((match-end 5) ; `ifndef
4628 (setq nest (1- nest)))
4629 ((match-end 6) ; `elsif
4640 (skip-chars-forward "^ \t")
4641 (verilog-forward-syntactic-ws)
4644 (skip-chars-forward "a-zA-Z0-9_")
4647 (if (> (count-lines (point) b) verilog-minimum-comment-distance)
4648 (insert (concat " // " else m " " (buffer-substring b e))))
4650 (insert " // unmatched `else, `elsif or `endif")
4653 (; Comment close case/class/function/task/module and named block
4654 (and (looking-at "\\<end")
4655 (or kill-existing-comment
4656 (not (save-excursion
4658 (search-backward "//" (point-at-bol) t)))))
4659 (let ((type (car indent-str)))
4660 (unless (eq type 'declaration)
4661 (unless (looking-at (concat "\\(" verilog-end-block-ordered-re "\\)[ \t]*:")) ; ignore named ends
4662 (if (looking-at verilog-end-block-ordered-re)
4664 (;- This is a case block; search back for the start of this case
4665 (match-end 1) ; of verilog-end-block-ordered-re
4668 (str "UNMATCHED!!"))
4670 (verilog-leap-to-head)
4672 ((looking-at "\\<randcase\\>")
4673 (setq str "randcase")
4675 ((looking-at "\\(\\(unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\)")
4676 (goto-char (match-end 0))
4677 (setq str (concat (match-string 0) " " (verilog-get-expr)))
4681 (if kill-existing-comment
4682 (verilog-kill-existing-comment))
4683 (delete-horizontal-space)
4684 (insert (concat " // " str ))
4685 (if err (ding 't))))
4687 (;- This is a begin..end block
4688 (match-end 2) ; of verilog-end-block-ordered-re
4689 (let ((str " // UNMATCHED !!")
4695 (verilog-leap-to-head)
4696 (setq there (point))
4697 (if (not (match-end 0))
4701 (if kill-existing-comment
4702 (verilog-kill-existing-comment))
4703 (delete-horizontal-space)
4707 (save-excursion (verilog-beg-of-defun) (point)))
4710 (;-- handle named block differently
4711 (looking-at verilog-named-block-re)
4712 (search-forward ":")
4713 (setq there (point))
4714 (setq str (verilog-get-expr))
4716 (setq str (concat " // block: " str )))
4718 ((verilog-in-case-region-p) ;-- handle case item differently
4720 (setq str (verilog-backward-case-item lim))
4721 (setq there (point))
4723 (setq str (concat " // case: " str )))
4725 (;- try to find "reason" for this begin
4729 ;; (verilog-backward-token)
4730 (verilog-beg-of-statement)
4734 ((looking-at verilog-endcomment-reason-re)
4735 (setq there (match-end 0))
4736 (setq cntx (concat (match-string 0) " "))
4742 (if (and (verilog-continued-line)
4743 (looking-at "\\<repeat\\>\\|\\<wait\\>\\|\\<always\\>"))
4745 (goto-char (match-end 0))
4746 (setq there (point))
4748 (concat " // " (match-string 0) " " (verilog-get-expr))))
4754 ( reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)\\|\\(assert\\)"))
4756 (while (verilog-re-search-backward reg nil 'move)
4758 ((match-end 1) ; begin
4759 (setq nest (1- nest)))
4760 ((match-end 2) ; end
4761 (setq nest (1+ nest)))
4765 (goto-char (match-end 0))
4766 (setq there (point))
4768 (setq str (verilog-get-expr))
4769 (setq str (concat " // else: !if" str ))
4774 (goto-char (match-end 0))
4775 (setq there (point))
4777 (setq str (verilog-get-expr))
4778 (setq str (concat " // else: !assert " str ))
4779 (throw 'skip 1)))))))))
4784 (reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)\\|\\(assert\\)"))
4786 (while (verilog-re-search-backward reg nil 'move)
4788 ((match-end 1) ; begin
4789 (setq nest (1- nest)))
4790 ((match-end 2) ; end
4791 (setq nest (1+ nest)))
4795 (goto-char (match-end 0))
4796 (setq there (point))
4798 (setq str (verilog-get-expr))
4799 (setq str (concat " // else: !if" str ))
4804 (goto-char (match-end 0))
4805 (setq there (point))
4807 (setq str (verilog-get-expr))
4808 (setq str (concat " // else: !assert " str ))
4809 (throw 'skip 1)))))))))
4811 (; always, always_comb, always_latch w/o @...
4813 (goto-char (match-end 0))
4814 (setq there (point))
4816 (setq str (concat " // " cntx )))
4818 (;- task/function/initial et cetera
4821 (goto-char (match-end 0))
4822 (setq there (point))
4824 (setq str (concat " // " cntx (verilog-get-expr))))
4827 (setq str " // auto-endcomment confused "))))
4830 (verilog-in-case-region-p) ;-- handle case item differently
4832 (setq there (point))
4834 (setq str (verilog-backward-case-item lim))))
4836 (setq str (concat " // case: " str )))
4838 ((verilog-in-fork-region-p)
4840 (setq str " // fork branch" ))
4842 ((looking-at "\\<end\\>")
4845 (verilog-forward-syntactic-ws)
4847 (setq str (verilog-get-expr))
4848 (setq str (concat " // " cntx str )))
4853 (if kill-existing-comment
4854 (verilog-kill-existing-comment))
4855 (delete-horizontal-space)
4857 (> (count-lines here there) verilog-minimum-comment-distance))
4861 (;- this is endclass, which can be nested
4862 (match-end 11) ; of verilog-end-block-ordered-re
4865 (reg "\\<\\(class\\)\\|\\(endclass\\)\\|\\(package\\|primitive\\|\\(macro\\)?module\\)\\>")
4869 (while (verilog-re-search-backward reg nil 'move)
4871 ((match-end 3) ; endclass
4873 (setq string "unmatched endclass")
4876 ((match-end 2) ; endclass
4877 (setq nest (1+ nest)))
4879 ((match-end 1) ; class
4880 (setq nest (1- nest))
4883 (goto-char (match-end 0))
4886 (skip-chars-forward "^ \t")
4887 (verilog-forward-ws&directives)
4890 (skip-chars-forward "a-zA-Z0-9_")
4892 (setq string (buffer-substring b e)))
4896 (if kill-existing-comment
4897 (verilog-kill-existing-comment))
4898 (delete-horizontal-space)
4899 (insert (concat " // " string ))))
4901 (; - this is end{function,generate,task,module,primitive,table,generate}
4902 ;; - which can not be nested.
4904 (let (string reg (name-re nil))
4906 (if kill-existing-comment
4908 (verilog-kill-existing-comment)))
4909 (delete-horizontal-space)
4912 ((match-end 5) ; of verilog-end-block-ordered-re
4913 (setq reg "\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
4914 (setq name-re "\\w+\\(?:\n\\|\\s-\\)*[(;]"))
4915 ((match-end 6) ; of verilog-end-block-ordered-re
4916 (setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
4917 (setq name-re "\\w+\\(?:\n\\|\\s-\\)*[(;]"))
4918 ((match-end 7) ; of verilog-end-block-ordered-re
4919 (setq reg "\\(\\<\\(macro\\)?module\\>\\)\\|\\<endmodule\\>"))
4920 ((match-end 8) ; of verilog-end-block-ordered-re
4921 (setq reg "\\(\\<primitive\\>\\)\\|\\(\\<\\(endprimitive\\|package\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4922 ((match-end 9) ; of verilog-end-block-ordered-re
4923 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<\\(endinterface\\|package\\|primitive\\|\\(macro\\)?module\\)\\>\\)"))
4924 ((match-end 10) ; of verilog-end-block-ordered-re
4925 (setq reg "\\(\\<package\\>\\)\\|\\(\\<\\(endpackage\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4926 ((match-end 11) ; of verilog-end-block-ordered-re
4927 (setq reg "\\(\\<class\\>\\)\\|\\(\\<\\(endclass\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4928 ((match-end 12) ; of verilog-end-block-ordered-re
4929 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<\\(endcovergroup\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4930 ((match-end 13) ; of verilog-end-block-ordered-re
4931 (setq reg "\\(\\<program\\>\\)\\|\\(\\<\\(endprogram\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4932 ((match-end 14) ; of verilog-end-block-ordered-re
4933 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<\\(endsequence\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4934 ((match-end 15) ; of verilog-end-block-ordered-re
4935 (setq reg "\\(\\<clocking\\>\\)\\|\\<endclocking\\>"))
4936 ((match-end 16) ; of verilog-end-block-ordered-re
4937 (setq reg "\\(\\<property\\>\\)\\|\\<endproperty\\>"))
4939 (t (error "Problem in verilog-set-auto-endcomments")))
4942 (verilog-re-search-backward reg nil 'move)
4946 (skip-chars-forward "^ \t")
4947 (verilog-forward-ws&directives)
4948 (if (looking-at "static\\|automatic")
4950 (goto-char (match-end 0))
4951 (verilog-forward-ws&directives)))
4952 (if (and name-re (verilog-re-search-forward name-re nil 'move))
4954 (goto-char (match-beginning 0))
4955 (verilog-forward-ws&directives)))
4958 (skip-chars-forward "a-zA-Z0-9_")
4960 (setq string (buffer-substring b e)))
4963 (setq string "unmatched end(function|task|module|primitive|interface|package|class|clocking)")))))
4965 (insert (concat " // " string )))
4968 (defun verilog-get-expr()
4969 "Grab expression at point, e.g., case ( a | b & (c ^d))."
4971 (verilog-forward-syntactic-ws)
4972 (skip-chars-forward " \t")
4978 (verilog-forward-syntactic-ws)
4979 (if (looking-at "(")
4982 (while (and (/= par 0)
4983 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
4986 (setq par (1+ par)))
4988 (setq par (1- par)))))))
4992 (while (and (/= par 0)
4993 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
4996 (setq par (1+ par)))
4998 (setq par (1- par)))))
5002 (while (and (/= par 0)
5003 (verilog-re-search-forward "\\(\\[\\)\\|\\(\\]\\)" nil 'move))
5006 (setq par (1+ par)))
5008 (setq par (1- par)))))
5009 (verilog-forward-syntactic-ws)
5010 (skip-chars-forward "^ \t\n\f")
5012 ((looking-at "/[/\\*]")
5015 (skip-chars-forward "^: \t\n\f")
5017 (str (buffer-substring b e)))
5018 (if (setq e (string-match "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
5019 (setq str (concat (substring str 0 e) "...")))
5022 (defun verilog-expand-vector ()
5023 "Take a signal vector on the current line and expand it to multiple lines.
5024 Useful for creating tri's and other expanded fields."
5026 (verilog-expand-vector-internal "[" "]"))
5028 (defun verilog-expand-vector-internal (bra ket)
5029 "Given BRA, the start brace and KET, the end brace, expand one line into many lines."
5032 (let ((signal-string (buffer-substring (point)
5034 (end-of-line) (point)))))
5038 "\\([0-9]*\\)\\(:[0-9]*\\|\\)\\(::[0-9---]*\\|\\)"
5040 "\\(.*\\)$") signal-string)
5041 (let* ((sig-head (match-string 1 signal-string))
5042 (vec-start (string-to-number (match-string 2 signal-string)))
5043 (vec-end (if (= (match-beginning 3) (match-end 3))
5046 (substring signal-string (1+ (match-beginning 3))
5049 (if (= (match-beginning 4) (match-end 4))
5052 (substring signal-string (+ 2 (match-beginning 4))
5054 (sig-tail (match-string 5 signal-string))
5059 (let ((tmp vec-start))
5060 (setq vec-start vec-end
5062 vec-range (- vec-range))))
5063 (if (< vec-end vec-start)
5064 (while (<= vec-end vec-start)
5065 (setq vec (append vec (list vec-start)))
5066 (setq vec-start (- vec-start vec-range)))
5067 (while (<= vec-start vec-end)
5068 (setq vec (append vec (list vec-start)))
5069 (setq vec-start (+ vec-start vec-range))))
5071 ;; Delete current line
5072 (delete-region (point) (progn (forward-line 0) (point)))
5076 (insert (concat sig-head bra
5077 (int-to-string (car vec)) ket sig-tail "\n"))
5078 (setq vec (cdr vec)))
5083 (defun verilog-strip-comments ()
5084 "Strip all comments from the Verilog code."
5086 (goto-char (point-min))
5087 (while (re-search-forward "//" nil t)
5088 (if (verilog-within-string)
5089 (re-search-forward "\"" nil t)
5090 (if (verilog-in-star-comment-p)
5091 (re-search-forward "\\*/" nil t)
5092 (let ((bpt (- (point) 2)))
5094 (delete-region bpt (point))))))
5096 (goto-char (point-min))
5097 (while (re-search-forward "/\\*" nil t)
5098 (if (verilog-within-string)
5099 (re-search-forward "\"" nil t)
5100 (let ((bpt (- (point) 2)))
5101 (re-search-forward "\\*/")
5102 (delete-region bpt (point))))))
5104 (defun verilog-one-line ()
5105 "Convert structural Verilog instances to occupy one line."
5107 (goto-char (point-min))
5108 (while (re-search-forward "\\([^;]\\)[ \t]*\n[ \t]*" nil t)
5109 (replace-match "\\1 " nil nil)))
5111 (defun verilog-linter-name ()
5112 "Return name of linter, either surelint or verilint."
5113 (let ((compile-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
5115 (lint-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
5117 (cond ((equal compile-word1 "surelint") `surelint)
5118 ((equal compile-word1 "verilint") `verilint)
5119 ((equal lint-word1 "surelint") `surelint)
5120 ((equal lint-word1 "verilint") `verilint)
5121 (t `surelint)))) ; back compatibility
5123 (defun verilog-lint-off ()
5124 "Convert a Verilog linter warning line into a disable statement.
5126 pci_bfm_null.v, line 46: Unused input: pci_rst_
5127 becomes a comment for the appropriate tool.
5129 The first word of the `compile-command' or `verilog-linter'
5130 variables is used to determine which product is being used.
5132 See \\[verilog-surelint-off] and \\[verilog-verilint-off]."
5134 (let ((linter (verilog-linter-name)))
5135 (cond ((equal linter `surelint)
5136 (verilog-surelint-off))
5137 ((equal linter `verilint)
5138 (verilog-verilint-off))
5139 (t (error "Linter name not set")))))
5141 (defvar compilation-last-buffer)
5142 (defvar next-error-last-buffer)
5144 (defun verilog-surelint-off ()
5145 "Convert a SureLint warning line into a disable statement.
5146 Run from Verilog source window; assumes there is a *compile* buffer
5147 with point set appropriately.
5150 WARNING [STD-UDDONX]: xx.v, line 8: output out is never assigned.
5152 // surefire lint_line_off UDDONX"
5154 (let ((buff (if (boundp 'next-error-last-buffer)
5155 next-error-last-buffer
5156 compilation-last-buffer)))
5157 (when (buffer-live-p buff)
5159 (switch-to-buffer buff)
5162 (looking-at "\\(INFO\\|WARNING\\|ERROR\\) \\[[^-]+-\\([^]]+\\)\\]: \\([^,]+\\), line \\([0-9]+\\): \\(.*\\)$")
5163 (let* ((code (match-string 2))
5164 (file (match-string 3))
5165 (line (match-string 4))
5166 (buffer (get-file-buffer file))
5171 (and (file-exists-p file)
5172 (find-file-noselect file)))
5174 (let* ((pop-up-windows t))
5175 (let ((name (expand-file-name
5177 (format "Find this error in: (default %s) "
5180 (if (file-directory-p name)
5181 (setq name (expand-file-name filename name)))
5183 (and (file-exists-p name)
5184 (find-file-noselect name))))))))
5185 (switch-to-buffer buffer)
5186 (goto-char (point-min))
5187 (forward-line (- (string-to-number line)))
5191 ((verilog-in-slash-comment-p)
5192 (re-search-backward "//")
5194 ((looking-at "// surefire lint_off_line ")
5195 (goto-char (match-end 0))
5196 (let ((lim (point-at-eol)))
5197 (if (re-search-forward code lim 'move)
5199 (insert (concat " " code)))))
5202 ((verilog-in-star-comment-p)
5203 (re-search-backward "/\\*")
5204 (insert (format " // surefire lint_off_line %6s" code )))
5206 (insert (format " // surefire lint_off_line %6s" code ))
5209 (defun verilog-verilint-off ()
5210 "Convert a Verilint warning line into a disable statement.
5213 (W240) pci_bfm_null.v, line 46: Unused input: pci_rst_
5215 //Verilint 240 off // WARNING: Unused input"
5219 (when (looking-at "\\(.*\\)([WE]\\([0-9A-Z]+\\)).*,\\s +line\\s +[0-9]+:\\s +\\([^:\n]+\\):?.*$")
5220 (replace-match (format
5221 ;; %3s makes numbers 1-999 line up nicely
5222 "\\1//Verilint %3s off // WARNING: \\3"
5225 (verilog-indent-line))))
5227 (defun verilog-auto-save-compile ()
5228 "Update automatics with \\[verilog-auto], save the buffer, and compile."
5230 (verilog-auto) ; Always do it for safety
5232 (compile compile-command))
5234 (defun verilog-preprocess (&optional command filename)
5235 "Preprocess the buffer, similar to `compile', but put output in Verilog-Mode.
5236 Takes optional COMMAND or defaults to `verilog-preprocessor', and
5237 FILENAME to find directory to run in, or defaults to `buffer-file-name'."
5240 (let ((default (verilog-expand-command verilog-preprocessor)))
5241 (set (make-local-variable `verilog-preprocessor)
5242 (read-from-minibuffer "Run Preprocessor (like this): "
5244 'verilog-preprocess-history default)))))
5245 (unless command (setq command (verilog-expand-command verilog-preprocessor)))
5246 (let* ((fontlocked (and (boundp 'font-lock-mode) font-lock-mode))
5247 (dir (file-name-directory (or filename buffer-file-name)))
5248 (cmd (concat "cd " dir "; " command)))
5249 (with-output-to-temp-buffer "*Verilog-Preprocessed*"
5250 (with-current-buffer (get-buffer "*Verilog-Preprocessed*")
5251 (insert (concat "// " cmd "\n"))
5252 (call-process shell-file-name nil t nil shell-command-switch cmd)
5254 ;; Without this force, it takes a few idle seconds
5255 ;; to get the color, which is very jarring
5256 (unless (fboundp 'font-lock-ensure)
5257 ;; We should use font-lock-ensure in preference to
5258 ;; font-lock-fontify-buffer, but IIUC the problem this is supposed to
5259 ;; solve only appears in Emacsen older than font-lock-ensure anyway.
5260 ;; So avoid bytecomp's interactive-only by going through intern.
5261 (when fontlocked (funcall (intern "font-lock-fontify-buffer"))))))))
5266 (defun verilog-warn (string &rest args)
5267 "Print a warning with `format' using STRING and optional ARGS."
5268 (apply 'message (concat "%%Warning: " string) args))
5270 (defun verilog-warn-error (string &rest args)
5271 "Call `error' using STRING and optional ARGS.
5272 If `verilog-warn-fatal' is non-nil, call `verilog-warn' instead."
5273 (if verilog-warn-fatal
5274 (apply 'error string args)
5275 (apply 'verilog-warn string args)))
5277 (defmacro verilog-batch-error-wrapper (&rest body)
5278 "Execute BODY and add error prefix to any errors found.
5279 This lets programs calling batch mode to easily extract error messages."
5280 `(let ((verilog-warn-fatal nil))
5284 (error "%%Error: %s%s" (error-message-string err)
5285 (if (featurep 'xemacs) "\n" "")))))) ; XEmacs forgets to add a newline
5287 (defun verilog-batch-execute-func (funref &optional no-save)
5288 "Internal processing of a batch command.
5289 Runs FUNREF on all command arguments.
5290 Save the result unless optional NO-SAVE is t."
5291 (verilog-batch-error-wrapper
5292 ;; Setting global variables like that is *VERY NASTY* !!! --Stef
5293 ;; However, this function is called only when Emacs is being used as
5294 ;; a standalone language instead of as an editor, so we'll live.
5296 ;; General globals needed
5297 (setq make-backup-files nil)
5298 (setq-default make-backup-files nil)
5299 (setq enable-local-variables t)
5300 (setq enable-local-eval t)
5301 (setq create-lockfiles nil)
5302 ;; Make sure any sub-files we read get proper mode
5303 (setq-default major-mode 'verilog-mode)
5304 ;; Ditto files already read in
5305 ;; Remember buffer list, so don't later pickup any verilog-getopt files
5306 (let ((orig-buffer-list (buffer-list)))
5308 (when (buffer-file-name buf)
5309 (with-current-buffer buf
5311 (verilog-auto-reeval-locals)
5312 (verilog-getopt-flags))))
5314 ;; Process the files
5315 (mapcar (lambda (buf)
5316 (when (buffer-file-name buf)
5318 (if (not (file-exists-p (buffer-file-name buf)))
5320 "File not found: %s" (buffer-file-name buf)))
5321 (message "Processing %s" (buffer-file-name buf))
5324 (when (and (not no-save)
5325 (buffer-modified-p)) ; Avoid "no changes to be saved"
5327 orig-buffer-list))))
5329 (defun verilog-batch-auto ()
5330 "For use with --batch, perform automatic expansions as a stand-alone tool.
5331 This sets up the appropriate Verilog mode environment, updates automatics
5332 with \\[verilog-auto] on all command-line files, and saves the buffers.
5333 For proper results, multiple filenames need to be passed on the command
5334 line in bottom-up order."
5335 (unless noninteractive
5336 (error "Use verilog-batch-auto only with --batch")) ; Otherwise we'd mess up buffer modes
5337 (verilog-batch-execute-func `verilog-auto))
5339 (defun verilog-batch-delete-auto ()
5340 "For use with --batch, perform automatic deletion as a stand-alone tool.
5341 This sets up the appropriate Verilog mode environment, deletes automatics
5342 with \\[verilog-delete-auto] on all command-line files, and saves the buffers."
5343 (unless noninteractive
5344 (error "Use verilog-batch-delete-auto only with --batch")) ; Otherwise we'd mess up buffer modes
5345 (verilog-batch-execute-func `verilog-delete-auto))
5347 (defun verilog-batch-delete-trailing-whitespace ()
5348 "For use with --batch, perform whitespace deletion as a stand-alone tool.
5349 This sets up the appropriate Verilog mode environment, removes
5350 whitespace with \\[verilog-delete-trailing-whitespace] on all
5351 command-line files, and saves the buffers."
5352 (unless noninteractive
5353 (error "Use verilog-batch-delete-trailing-whitespace only with --batch")) ; Otherwise we'd mess up buffer modes
5354 (verilog-batch-execute-func `verilog-delete-trailing-whitespace))
5356 (defun verilog-batch-diff-auto ()
5357 "For use with --batch, perform automatic differences as a stand-alone tool.
5358 This sets up the appropriate Verilog mode environment, expand automatics
5359 with \\[verilog-diff-auto] on all command-line files, and reports an error
5360 if any differences are observed. This is appropriate for adding to regressions
5361 to insure automatics are always properly maintained."
5362 (unless noninteractive
5363 (error "Use verilog-batch-diff-auto only with --batch")) ; Otherwise we'd mess up buffer modes
5364 (verilog-batch-execute-func `verilog-diff-auto t))
5366 (defun verilog-batch-inject-auto ()
5367 "For use with --batch, perform automatic injection as a stand-alone tool.
5368 This sets up the appropriate Verilog mode environment, injects new automatics
5369 with \\[verilog-inject-auto] on all command-line files, and saves the buffers.
5370 For proper results, multiple filenames need to be passed on the command
5371 line in bottom-up order."
5372 (unless noninteractive
5373 (error "Use verilog-batch-inject-auto only with --batch")) ; Otherwise we'd mess up buffer modes
5374 (verilog-batch-execute-func `verilog-inject-auto))
5376 (defun verilog-batch-indent ()
5377 "For use with --batch, reindent an entire file as a stand-alone tool.
5378 This sets up the appropriate Verilog mode environment, calls
5379 \\[verilog-indent-buffer] on all command-line files, and saves the buffers."
5380 (unless noninteractive
5381 (error "Use verilog-batch-indent only with --batch")) ; Otherwise we'd mess up buffer modes
5382 (verilog-batch-execute-func `verilog-indent-buffer))
5386 (defconst verilog-indent-alist
5387 '((block . (+ ind verilog-indent-level))
5388 (case . (+ ind verilog-case-indent))
5389 (cparenexp . (+ ind verilog-indent-level))
5390 (cexp . (+ ind verilog-cexp-indent))
5391 (defun . verilog-indent-level-module)
5392 (declaration . verilog-indent-level-declaration)
5393 (directive . (verilog-calculate-indent-directive))
5394 (tf . verilog-indent-level)
5395 (behavioral . (+ verilog-indent-level-behavioral verilog-indent-level-module))
5398 (comment . (verilog-comment-indent))
5402 (defun verilog-continued-line-1 (lim)
5403 "Return true if this is a continued line.
5404 Set point to where line starts. Limit search to point LIM."
5405 (let ((continued 't))
5406 (if (eq 0 (forward-line -1))
5409 (verilog-backward-ws&directives lim)
5411 (setq continued nil)
5412 (setq continued (verilog-backward-token))))
5413 (setq continued nil))
5416 (defun verilog-calculate-indent ()
5417 "Calculate the indent of the current Verilog line.
5418 Examine previous lines. Once a line is found that is definitive as to the
5419 type of the current line, return that lines' indent level and its type.
5420 Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
5422 (let* ((starting_position (point))
5423 (case-fold-search nil)
5425 (begin (looking-at "[ \t]*begin\\>"))
5426 (lim (save-excursion (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)" nil t)))
5428 (type (catch 'nesting
5429 ;; Keep working backwards until we can figure out
5430 ;; what type of statement this is.
5431 ;; Basically we need to figure out
5432 ;; 1) if this is a continuation of the previous line;
5433 ;; 2) are we in a block scope (begin..end)
5435 ;; if we are in a comment, done.
5436 (if (verilog-in-star-comment-p)
5437 (throw 'nesting 'comment))
5439 ;; if we have a directive, done.
5440 (if (save-excursion (beginning-of-line)
5441 (and (looking-at verilog-directive-re-1)
5442 (not (or (looking-at "[ \t]*`[ou]vm_")
5443 (looking-at "[ \t]*`vmm_")))))
5444 (throw 'nesting 'directive))
5445 ;; indent structs as if there were module level
5446 (setq structres (verilog-in-struct-nested-p))
5447 (cond ((not structres) nil)
5448 ;;((and structres (equal (char-after) ?\})) (throw 'nesting 'struct-close))
5449 ((> structres 0) (throw 'nesting 'nested-struct))
5450 ((= structres 0) (throw 'nesting 'block))
5453 ;; if we are in a parenthesized list, and the user likes to indent these, return.
5454 ;; unless we are in the newfangled coverpoint or constraint blocks
5456 verilog-indent-lists
5458 (not (verilog-in-coverage-p))
5461 (throw 'nesting 'block)))
5463 ;; See if we are continuing a previous line
5465 ;; trap out if we crawl off the top of the buffer
5466 (if (bobp) (throw 'nesting 'cpp))
5468 (if (and (verilog-continued-line-1 lim)
5469 (or (not (verilog-in-coverage-p))
5470 (looking-at verilog-in-constraint-re) )) ; may still get hosed if concat in constraint
5473 (not (looking-at verilog-complete-reg))
5474 (verilog-continued-line-1 lim))
5475 (progn (goto-char sp)
5476 (throw 'nesting 'cexp))
5479 (if (and (verilog-in-coverage-p)
5480 (looking-at verilog-in-constraint-re))
5483 (skip-chars-forward " \t")
5484 (throw 'nesting 'constraint)))
5486 (not verilog-indent-begin-after-if)
5487 (looking-at verilog-no-indent-begin-re))
5490 (skip-chars-forward " \t")
5491 (throw 'nesting 'statement))
5493 (throw 'nesting 'cexp))))
5494 ;; not a continued line
5495 (goto-char starting_position))
5497 (if (looking-at "\\<else\\>")
5498 ;; search back for governing if, striding across begin..end pairs
5501 (while (verilog-re-search-backward verilog-ends-re nil 'move)
5503 ((match-end 1) ; else, we're in deep
5504 (setq elsec (1+ elsec)))
5506 (setq elsec (1- elsec))
5508 (if verilog-align-ifelse
5509 (throw 'nesting 'statement)
5510 (progn ; back up to first word on this line
5512 (verilog-forward-syntactic-ws)
5513 (throw 'nesting 'statement)))))
5514 ((match-end 3) ; assert block
5515 (setq elsec (1- elsec))
5516 (verilog-beg-of-statement) ; doesn't get to beginning
5517 (if (looking-at verilog-property-re)
5518 (throw 'nesting 'statement) ; We don't need an endproperty for these
5519 (throw 'nesting 'block) ; We still need an endproperty
5522 ;; try to leap back to matching outward block by striding across
5523 ;; indent level changing tokens then immediately
5524 ;; previous line governs indentation.
5525 (let (( reg) (nest 1))
5526 ;; verilog-ends => else|if|end|join(_any|_none|)|endcase|endclass|endtable|endspecify|endfunction|endtask|endgenerate|endgroup
5528 ((match-end 4) ; end
5529 ;; Search back for matching begin
5530 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
5531 ((match-end 5) ; endcase
5532 ;; Search back for matching case
5533 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
5534 ((match-end 6) ; endfunction
5535 ;; Search back for matching function
5536 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
5537 ((match-end 7) ; endtask
5538 ;; Search back for matching task
5539 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
5540 ((match-end 8) ; endspecify
5541 ;; Search back for matching specify
5542 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
5543 ((match-end 9) ; endtable
5544 ;; Search back for matching table
5545 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
5546 ((match-end 10) ; endgenerate
5547 ;; Search back for matching generate
5548 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
5549 ((match-end 11) ; joins
5550 ;; Search back for matching fork
5551 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|none\\)?\\>\\)" ))
5552 ((match-end 12) ; class
5553 ;; Search back for matching class
5554 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
5555 ((match-end 13) ; covergroup
5556 ;; Search back for matching covergroup
5557 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" )))
5559 (while (verilog-re-search-backward reg nil 'move)
5561 ((match-end 1) ; begin
5562 (setq nest (1- nest))
5565 ((match-end 2) ; end
5566 (setq nest (1+ nest)))))
5568 (throw 'nesting (verilog-calc-1)))
5572 ;; Return type of block and indent level.
5575 (if (> par 0) ; Unclosed Parenthesis
5576 (list 'cparenexp par)
5579 (list type (verilog-case-indent-level)))
5580 ((eq type 'statement)
5581 (list type (current-column)))
5584 ((eq type 'constraint)
5585 (list 'block (current-column)))
5586 ((eq type 'nested-struct)
5587 (list 'block structres))
5589 (list type (verilog-current-indent-level))))))))
5591 (defun verilog-wai ()
5592 "Show matching nesting block for debugging."
5595 (let* ((type (verilog-calc-1))
5597 ;; Return type of block and indent level.
5601 verilog-indent-lists
5602 (not(or (verilog-in-coverage-p)
5603 (verilog-in-struct-p)))
5608 (setq depth (verilog-case-indent-level)))
5609 ((eq type 'statement)
5610 (setq depth (current-column)))
5614 (setq depth (verilog-current-indent-level)))))
5615 (message "You are at nesting %s depth %d" type depth))))
5617 (defun verilog-calc-1 ()
5619 (let ((re (concat "\\({\\|}\\|" verilog-indent-re "\\)"))
5620 (inconstraint (verilog-in-coverage-p)))
5621 (while (verilog-re-search-backward re nil 'move)
5624 ((equal (char-after) ?\{)
5625 ;; block type returned based on outer constraint { or inner
5626 (if (verilog-at-constraint-p)
5628 (beginning-of-line nil)
5629 (skip-chars-forward " \t")
5630 (throw 'nesting 'constraint))
5632 (throw 'nesting 'statement)))))
5633 ((equal (char-after) ?\})
5635 (there (verilog-at-close-constraint-p)))
5636 (if there ; we are at the } that closes a constraint. Find the { that opens it
5638 (if (> (verilog-in-paren-count) 0)
5640 (setq par-pos (verilog-parenthesis-depth))
5645 (backward-char 1)))))))
5647 ((looking-at verilog-beg-block-re-ordered)
5649 ((match-end 2) ; *sigh* could be "unique case" or "priority casex"
5650 (let ((here (point)))
5651 (verilog-beg-of-statement)
5652 (if (looking-at verilog-extended-case-re)
5653 (throw 'nesting 'case)
5655 (throw 'nesting 'case))
5657 ((match-end 4) ; *sigh* could be "disable fork"
5658 (let ((here (point)))
5659 (verilog-beg-of-statement)
5660 (if (looking-at verilog-disable-fork-re)
5661 t ; this is a normal statement
5662 (progn ; or is fork, starts a new block
5664 (throw 'nesting 'block)))))
5666 ((match-end 27) ; *sigh* might be a clocking declaration
5667 (let ((here (point)))
5668 (if (verilog-in-paren)
5669 t ; this is a normal statement
5670 (progn ; or is fork, starts a new block
5672 (throw 'nesting 'block)))))
5674 ;; need to consider typedef struct here...
5675 ((looking-at "\\<class\\|struct\\|function\\|task\\>")
5676 ;; *sigh* These words have an optional prefix:
5677 ;; extern {virtual|protected}? function a();
5678 ;; typedef class foo;
5679 ;; and we don't want to confuse this with
5684 (verilog-beg-of-statement)
5686 ((looking-at verilog-dpi-import-export-re)
5687 (throw 'continue 'foo))
5688 ((looking-at "\\<pure\\>\\s-+\\<virtual\\>\\s-+\\(?:\\<\\(local\\|protected\\|static\\)\\>\\s-+\\)?\\<\\(function\\|task\\)\\>\\s-+")
5689 (throw 'nesting 'statement))
5690 ((looking-at verilog-beg-block-re-ordered)
5691 (throw 'nesting 'block))
5693 (throw 'nesting 'defun))))
5696 ((looking-at "\\<property\\>")
5698 ;; {assert|assume|cover} property (); are complete
5699 ;; and could also be labeled: - foo: assert property
5701 ;; property ID () ... needs end_property
5702 (verilog-beg-of-statement)
5703 (if (looking-at verilog-property-re)
5704 (throw 'continue 'statement) ; We don't need an endproperty for these
5705 (throw 'nesting 'block) ;We still need an endproperty
5708 (t (throw 'nesting 'block))))
5710 ((looking-at verilog-end-block-re)
5711 (verilog-leap-to-head)
5712 (if (verilog-in-case-region-p)
5714 (verilog-leap-to-case-head)
5715 (if (looking-at verilog-extended-case-re)
5716 (throw 'nesting 'case)))))
5718 ((looking-at verilog-defun-level-re)
5719 (if (looking-at verilog-defun-level-generate-only-re)
5720 (if (or (verilog-in-generate-region-p)
5721 (verilog-in-deferred-immediate-final-p))
5722 (throw 'continue 'foo) ; always block in a generate - keep looking
5723 (throw 'nesting 'defun))
5724 (throw 'nesting 'defun)))
5726 ((looking-at verilog-cpp-level-re)
5727 (throw 'nesting 'cpp))
5730 (throw 'nesting 'cpp)))))
5732 (throw 'nesting 'cpp))))
5734 (defun verilog-calculate-indent-directive ()
5735 "Return indentation level for directive.
5736 For speed, the searcher looks at the last directive, not the indent
5737 of the appropriate enclosing block."
5738 (let ((base -1) ; Indent of the line that determines our indentation
5739 (ind 0)) ; Relative offset caused by other directives (like `endif on same line as `else)
5740 ;; Start at current location, scan back for another directive
5744 (while (and (< base 0)
5745 (verilog-re-search-backward verilog-directive-re nil t))
5746 (cond ((save-excursion (skip-chars-backward " \t") (bolp))
5747 (setq base (current-indentation))))
5748 (cond ((and (looking-at verilog-directive-end) (< base 0)) ; Only matters when not at BOL
5749 (setq ind (- ind verilog-indent-level-directive)))
5750 ((and (looking-at verilog-directive-middle) (>= base 0)) ; Only matters when at BOL
5751 (setq ind (+ ind verilog-indent-level-directive)))
5752 ((looking-at verilog-directive-begin)
5753 (setq ind (+ ind verilog-indent-level-directive)))))
5754 ;; Adjust indent to starting indent of critical line
5755 (setq ind (max 0 (+ ind base))))
5759 (skip-chars-forward " \t")
5760 (cond ((or (looking-at verilog-directive-middle)
5761 (looking-at verilog-directive-end))
5762 (setq ind (max 0 (- ind verilog-indent-level-directive))))))
5765 (defun verilog-leap-to-case-head ()
5768 (verilog-re-search-backward
5770 "\\(\\<randcase\\>\\|\\(\\<unique0?\\s-+\\|priority\\s-+\\)?\\<case[xz]?\\>\\)"
5771 "\\|\\(\\<endcase\\>\\)" )
5775 (let ((here (point)))
5776 (verilog-beg-of-statement)
5777 (unless (looking-at verilog-extended-case-re)
5779 (setq nest (1- nest)))
5781 (setq nest (1+ nest)))
5786 (defun verilog-leap-to-head ()
5787 "Move point to the head of this block.
5788 Jump from end to matching begin, from endcase to matching case, and so on."
5794 ((looking-at "\\<end\\>")
5795 ;; 1: Search back for matching begin
5796 (setq reg (concat "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|"
5797 "\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))
5798 ((looking-at "\\<endtask\\>")
5799 ;; 2: Search back for matching task
5800 (setq reg "\\(\\<task\\>\\)\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)+\\<task\\>\\)")
5802 ((looking-at "\\<endcase\\>")
5804 (verilog-leap-to-case-head) )
5805 (setq reg nil) ; to force skip
5808 ((looking-at "\\<join\\(_any\\|_none\\)?\\>")
5809 ;; 4: Search back for matching fork
5810 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
5811 ((looking-at "\\<endclass\\>")
5812 ;; 5: Search back for matching class
5813 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
5814 ((looking-at "\\<endtable\\>")
5815 ;; 6: Search back for matching table
5816 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
5817 ((looking-at "\\<endspecify\\>")
5818 ;; 7: Search back for matching specify
5819 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
5820 ((looking-at "\\<endfunction\\>")
5821 ;; 8: Search back for matching function
5822 (setq reg "\\(\\<function\\>\\)\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)+\\<function\\>\\)")
5824 ;;(setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
5825 ((looking-at "\\<endgenerate\\>")
5826 ;; 8: Search back for matching generate
5827 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
5828 ((looking-at "\\<endgroup\\>")
5829 ;; 10: Search back for matching covergroup
5830 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
5831 ((looking-at "\\<endproperty\\>")
5832 ;; 11: Search back for matching property
5833 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
5834 ((looking-at verilog-uvm-end-re)
5835 ;; 12: Search back for matching sequence
5836 (setq reg (concat "\\(" verilog-uvm-begin-re "\\|" verilog-uvm-end-re "\\)")))
5837 ((looking-at verilog-ovm-end-re)
5838 ;; 12: Search back for matching sequence
5839 (setq reg (concat "\\(" verilog-ovm-begin-re "\\|" verilog-ovm-end-re "\\)")))
5840 ((looking-at verilog-vmm-end-re)
5841 ;; 12: Search back for matching sequence
5842 (setq reg (concat "\\(" verilog-vmm-begin-re "\\|" verilog-vmm-end-re "\\)")))
5843 ((looking-at "\\<endinterface\\>")
5844 ;; 12: Search back for matching interface
5845 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<endinterface\\>\\)" ))
5846 ((looking-at "\\<endsequence\\>")
5847 ;; 12: Search back for matching sequence
5848 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" ))
5849 ((looking-at "\\<endclocking\\>")
5850 ;; 12: Search back for matching clocking
5851 (setq reg "\\(\\<clocking\\)\\|\\(\\<endclocking\\>\\)" )))
5854 (if (eq nesting 'yes)
5856 (while (verilog-re-search-backward reg nil 'move)
5858 ((match-end 1) ; begin
5859 (if (looking-at "fork")
5860 (let ((here (point)))
5861 (verilog-beg-of-statement)
5862 (unless (looking-at verilog-disable-fork-re)
5864 (setq nest (1- nest))))
5865 (setq nest (1- nest)))
5867 ;; Now previous line describes syntax
5872 ((match-end 2) ; end
5873 (setq nest (1+ nest)))
5875 ;; endcase, jump to case
5877 (setq nest (1+ nest))
5879 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
5881 ;; join, jump to fork
5883 (setq nest (1+ nest))
5885 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
5889 (verilog-re-search-backward reg nil 'move)
5890 (match-end 1)) ; task -> could be virtual and/or protected
5892 (verilog-beg-of-statement)
5894 (throw 'skip 1)))))))
5896 (defun verilog-continued-line ()
5897 "Return true if this is a continued line.
5898 Set point to where line starts."
5899 (let ((continued 't))
5900 (if (eq 0 (forward-line -1))
5903 (verilog-backward-ws&directives)
5905 (setq continued nil)
5906 (while (and continued
5908 (skip-chars-backward " \t")
5910 (setq continued (verilog-backward-token)))))
5911 (setq continued nil))
5914 (defun verilog-backward-token ()
5915 "Step backward token, returning true if this is a continued line."
5917 (verilog-backward-syntactic-ws)
5921 (;-- Anything ending in a ; is complete
5922 (= (preceding-char) ?\;)
5924 (; If a "}" is prefixed by a ";", then this is a complete statement
5925 ;; i.e.: constraint foo { a = b; }
5926 (= (preceding-char) ?\})
5929 (not(verilog-at-close-constraint-p))))
5930 (;-- constraint foo { a = b }
5931 ;; is a complete statement. *sigh*
5932 (= (preceding-char) ?\{)
5935 (not (verilog-at-constraint-p))))
5937 (= (preceding-char) ?\")
5939 (verilog-skip-backward-comment-or-string)
5943 (= (preceding-char) ?\])
5945 (verilog-backward-open-bracket)
5948 (;-- Could be 'case (foo)' or 'always @(bar)' which is complete
5949 ;; also could be simply '@(foo)'
5951 ;; (b, ... which ISN'T complete
5952 ;; Do we need this???
5953 (= (preceding-char) ?\))
5956 (verilog-backward-up-list 1)
5957 (verilog-backward-syntactic-ws)
5958 (let ((back (point)))
5962 ((looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|case\\(\\|[xz]\\)\\|for\\(\\|each\\|ever\\)\\|i\\(f\\|nitial\\)\\|repeat\\|while\\)\\>")
5963 (not (looking-at "\\<randcase\\>\\|\\<case[xz]?\\>[^:]")))
5964 ((looking-at verilog-uvm-statement-re)
5966 ((looking-at verilog-uvm-begin-re)
5968 ((looking-at verilog-uvm-end-re)
5970 ((looking-at verilog-ovm-statement-re)
5972 ((looking-at verilog-ovm-begin-re)
5974 ((looking-at verilog-ovm-end-re)
5976 ;; JBA find VMM macros
5977 ((looking-at verilog-vmm-statement-re)
5979 ((looking-at verilog-vmm-begin-re)
5981 ((looking-at verilog-vmm-end-re)
5983 ;; JBA trying to catch macro lines with no ; at end
5984 ((looking-at "\\<`")
5989 ((= (preceding-char) ?\@)
5992 (verilog-backward-token)
5993 (not (looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|initial\\|while\\)\\>"))))
5994 ((= (preceding-char) ?\#)
5998 (;-- any of begin|initial|while are complete statements; 'begin : foo' is also complete
6001 (while (or (= (preceding-char) ?\_)
6002 (= (preceding-char) ?\@)
6003 (= (preceding-char) ?\.))
6006 ((looking-at "\\<else\\>")
6008 ((looking-at verilog-behavioral-block-beg-re)
6010 ((looking-at verilog-indent-re)
6015 (verilog-backward-syntactic-ws)
6017 ((= (preceding-char) ?\:)
6019 (verilog-backward-syntactic-ws)
6021 (if (looking-at verilog-nameable-item-re )
6024 ((= (preceding-char) ?\#)
6027 ((= (preceding-char) ?\`)
6035 (defun verilog-backward-syntactic-ws ()
6036 "Move backwards putting point after first non-whitespace non-comment."
6037 (verilog-skip-backward-comments)
6038 (forward-comment (- (buffer-size))))
6040 (defun verilog-backward-syntactic-ws-quick ()
6041 "As with `verilog-backward-syntactic-ws' but use `verilog-scan' cache."
6042 (while (cond ((bobp)
6044 ((< (skip-syntax-backward " ") 0)
6046 ((eq (preceding-char) ?\n) ; \n's terminate // so aren't space syntax
6049 ((or (verilog-inside-comment-or-string-p (1- (point)))
6050 (verilog-inside-comment-or-string-p (point)))
6051 (re-search-backward "[/\"]" nil t) ; Only way a comment or quote can begin
6054 (defun verilog-forward-syntactic-ws ()
6055 (verilog-skip-forward-comment-p)
6056 (forward-comment (buffer-size)))
6058 (defun verilog-backward-ws&directives (&optional bound)
6059 "Backward skip over syntactic whitespace and compiler directives for Emacs 19.
6060 Optional BOUND limits search."
6062 (let* ((bound (or bound (point-min)))
6065 (if (< bound (point))
6067 (let ((state (save-excursion (verilog-syntax-ppss))))
6069 ((nth 7 state) ; in // comment
6070 (verilog-re-search-backward "//" nil 'move)
6071 (skip-chars-backward "/"))
6072 ((nth 4 state) ; in /* */ comment
6073 (verilog-re-search-backward "/\\*" nil 'move))))
6074 (narrow-to-region bound (point))
6075 (while (/= here (point))
6077 (verilog-skip-backward-comments)
6081 ;; for as long as we're right after a continued line, keep moving up
6082 (while (and (verilog-looking-back "\\\\[\n\r\f]" nil)
6085 ((and verilog-highlight-translate-off
6086 (verilog-within-translate-off))
6087 (verilog-back-to-start-translate-off (point-min)))
6088 ((looking-at verilog-directive-re-1)
6092 (if p (goto-char p))))))))
6094 (defun verilog-forward-ws&directives (&optional bound)
6095 "Forward skip over syntactic whitespace and compiler directives for Emacs 19.
6096 Optional BOUND limits search."
6098 (let* ((bound (or bound (point-max)))
6101 (if (> bound (point))
6103 (let ((state (save-excursion (verilog-syntax-ppss))))
6105 ((nth 7 state) ; in // comment
6108 (skip-chars-forward " \t\n\f")
6110 ((nth 4 state) ; in /* */ comment
6111 (verilog-re-search-forward "\\*/\\s-*" nil 'move))))
6112 (narrow-to-region (point) bound)
6113 (while (/= here (point))
6116 (forward-comment (buffer-size))
6117 (and (looking-at "\\s-*(\\*.*\\*)\\s-*") ; Attribute
6118 (goto-char (match-end 0)))
6121 (if (looking-at verilog-directive-re-1)
6124 (beginning-of-line 2))))))))
6126 (defun verilog-in-comment-p ()
6127 "Return true if in a star or // comment."
6128 (let ((state (save-excursion (verilog-syntax-ppss))))
6129 (or (nth 4 state) (nth 7 state))))
6131 (defun verilog-in-star-comment-p ()
6132 "Return true if in a star comment."
6133 (let ((state (save-excursion (verilog-syntax-ppss))))
6135 (nth 4 state) ; t if in a comment of style a // or b /**/
6137 (nth 7 state) ; t if in a comment of style b /**/
6140 (defun verilog-in-slash-comment-p ()
6141 "Return true if in a slash comment."
6142 (let ((state (save-excursion (verilog-syntax-ppss))))
6145 (defun verilog-in-comment-or-string-p ()
6146 "Return true if in a string or comment."
6147 (let ((state (save-excursion (verilog-syntax-ppss))))
6148 (or (nth 3 state) (nth 4 state) (nth 7 state)))) ; Inside string or comment)
6150 (defun verilog-in-attribute-p ()
6151 "Return true if point is in an attribute (* [] attribute *)."
6154 (verilog-re-search-backward "\\((\\*\\)\\|\\(\\*)\\)" nil 'move)
6157 (progn (goto-char (match-end 1))
6158 (not (looking-at "\\s-*)")))
6161 (progn (goto-char (match-beginning 2))
6162 (not (looking-at "(\\s-*")))
6166 (defun verilog-in-parameter-p ()
6167 "Return true if point is in a parameter assignment #( p1=1, p2=5)."
6170 (verilog-re-search-backward "\\(#(\\)\\|\\()\\)" nil 'move)
6171 (numberp (match-beginning 1)))))
6173 (defun verilog-in-escaped-name-p ()
6174 "Return true if in an escaped name."
6177 (skip-chars-backward "^ \t\n\f")
6178 (if (equal (char-after (point) ) ?\\ )
6182 (defun verilog-in-directive-p ()
6183 "Return true if in a directive."
6186 (looking-at verilog-directive-re-1)))
6188 (defun verilog-in-parenthesis-p ()
6189 "Return true if in a ( ) expression (but not { } or [ ])."
6192 (verilog-re-search-backward "\\((\\)\\|\\()\\)" nil 'move)
6193 (numberp (match-beginning 1)))))
6195 (defun verilog-in-paren ()
6196 "Return true if in a parenthetical expression.
6197 May cache result using `verilog-syntax-ppss'."
6198 (let ((state (save-excursion (verilog-syntax-ppss))))
6199 (> (nth 0 state) 0 )))
6201 (defun verilog-in-paren-count ()
6202 "Return paren depth, floor to 0.
6203 May cache result using `verilog-syntax-ppss'."
6204 (let ((state (save-excursion (verilog-syntax-ppss))))
6205 (if (> (nth 0 state) 0)
6209 (defun verilog-in-paren-quick ()
6210 "Return true if in a parenthetical expression.
6211 Always starts from `point-min', to allow inserts with hooks disabled."
6212 ;; The -quick refers to its use alongside the other -quick functions,
6213 ;; not that it's likely to be faster than verilog-in-paren.
6214 (let ((state (save-excursion (parse-partial-sexp (point-min) (point)))))
6215 (> (nth 0 state) 0 )))
6217 (defun verilog-in-struct-p ()
6218 "Return true if in a struct declaration."
6221 (if (verilog-in-paren)
6223 (verilog-backward-up-list 1)
6224 (verilog-at-struct-p)
6228 (defun verilog-in-struct-nested-p ()
6229 "Return nil for not in struct.
6230 Return 0 for in non-nested struct.
6231 Return >0 for nested struct."
6235 (if (verilog-in-paren)
6237 (verilog-backward-up-list 1)
6238 (setq col (verilog-at-struct-mv-p))
6240 (if (verilog-in-struct-p) (current-column) 0)))
6243 (defun verilog-in-coverage-p ()
6244 "Return true if in a constraint or coverpoint expression."
6247 (if (verilog-in-paren)
6249 (verilog-backward-up-list 1)
6250 (verilog-at-constraint-p)
6254 (defun verilog-at-close-constraint-p ()
6255 "If at the } that closes a constraint or covergroup, return true."
6257 (equal (char-after) ?\})
6258 (verilog-in-coverage-p))
6261 (verilog-backward-ws&directives)
6262 (if (or (equal (char-before) ?\;)
6263 (equal (char-before) ?\}) ; can end with inner constraint { } block or ;
6264 (equal (char-before) ?\{)) ; empty constraint block
6268 (defun verilog-at-constraint-p ()
6269 "If at the { of a constraint or coverpoint definition, return true, moving point to constraint."
6273 (equal (char-after) ?\{)
6275 (progn (backward-char 1)
6276 (verilog-backward-ws&directives)
6278 (or (equal (char-before) ?\{) ; empty case
6279 (equal (char-before) ?\;)
6280 (equal (char-before) ?\}))
6281 ;; skip what looks like bus repetition operator {#{
6282 (not (string-match "^{\\s-*[0-9]+\\s-*{" (buffer-substring p (point)))))))))
6284 (let ( (pt (point)) (pass 0))
6285 (verilog-backward-ws&directives)
6286 (verilog-backward-token)
6287 (if (looking-at (concat "\\<constraint\\|coverpoint\\|cross\\|with\\>\\|" verilog-in-constraint-re))
6288 (progn (setq pass 1)
6289 (if (looking-at "\\<with\\>")
6290 (progn (verilog-backward-ws&directives)
6291 (beginning-of-line) ; 1
6292 (verilog-forward-ws&directives)
6294 (verilog-beg-of-statement)
6296 ;; if first word token not keyword, it maybe the instance name
6297 ;; check next word token
6298 (if (looking-at "\\<\\w+\\>\\|\\s-*(\\s-*\\S-+")
6299 (progn (verilog-beg-of-statement)
6300 (if (looking-at (concat "\\<\\(constraint\\|"
6301 "\\(?:\\w+\\s-*:\\s-*\\)?\\(coverpoint\\|cross\\)"
6302 "\\|with\\)\\>\\|" verilog-in-constraint-re))
6305 (progn (goto-char pt) nil) 1)))
6309 (defun verilog-at-struct-p ()
6310 "If at the { of a struct, return true, not moving point."
6312 (if (and (equal (char-after) ?\{)
6313 (verilog-backward-token))
6314 (looking-at "\\<struct\\|union\\|packed\\|\\(un\\)?signed\\>")
6317 (defun verilog-at-struct-mv-p ()
6318 "If at the { of a struct, return true, moving point to struct."
6320 (if (and (equal (char-after) ?\{)
6321 (verilog-backward-token))
6322 (if (looking-at "\\<struct\\|union\\|packed\\|\\(un\\)?signed\\>")
6323 (progn (verilog-beg-of-statement) (point))
6324 (progn (goto-char pt) nil))
6325 (progn (goto-char pt) nil))))
6327 (defun verilog-at-close-struct-p ()
6328 "If at the } that closes a struct, return true."
6330 (equal (char-after) ?\})
6331 (verilog-in-struct-p))
6334 (if (looking-at "}\\(?:\\s-*\\w+\\s-*\\)?;") 1))
6338 (defun verilog-parenthesis-depth ()
6339 "Return non zero if in parenthetical-expression."
6340 (save-excursion (nth 1 (verilog-syntax-ppss))))
6343 (defun verilog-skip-forward-comment-or-string ()
6344 "Return true if in a string or comment."
6345 (let ((state (save-excursion (verilog-syntax-ppss))))
6347 ((nth 3 state) ;Inside string
6348 (search-forward "\"")
6350 ((nth 7 state) ;Inside // comment
6353 ((nth 4 state) ;Inside any comment (hence /**/)
6354 (search-forward "*/"))
6358 (defun verilog-skip-backward-comment-or-string ()
6359 "Return true if in a string or comment."
6360 (let ((state (save-excursion (verilog-syntax-ppss))))
6362 ((nth 3 state) ;Inside string
6363 (search-backward "\"")
6365 ((nth 7 state) ;Inside // comment
6366 (search-backward "//")
6367 (skip-chars-backward "/")
6369 ((nth 4 state) ;Inside /* */ comment
6370 (search-backward "/*")
6375 (defun verilog-skip-backward-comments ()
6376 "Return true if a comment was skipped."
6380 (let ((state (save-excursion (verilog-syntax-ppss))))
6382 ((nth 7 state) ;Inside // comment
6383 (search-backward "//")
6384 (skip-chars-backward "/")
6385 (skip-chars-backward " \t\n\f")
6387 ((nth 4 state) ;Inside /* */ comment
6388 (search-backward "/*")
6389 (skip-chars-backward " \t\n\f")
6392 (= (char-before) ?\/)
6393 (= (char-before (1- (point))) ?\*))
6394 (goto-char (- (point) 2))
6395 t) ; Let nth 4 state handle the rest
6397 ;;(verilog-looking-back "\\*)" nil) ;; super slow, use two char-before instead
6398 (= (char-before) ?\))
6399 (= (char-before (1- (point))) ?\*)
6400 (not (verilog-looking-back "(\\s-*\\*)" nil))) ;; slow but unlikely to be called
6401 (goto-char (- (point) 2))
6402 (if (search-backward "(*" nil t)
6404 (skip-chars-backward " \t\n\f")
6407 (goto-char (+ (point) 2))
6410 (/= (skip-chars-backward " \t\n\f") 0))))))))
6412 (defun verilog-skip-forward-comment-p ()
6413 "If in comment, move to end and return true."
6415 (state (save-excursion (verilog-syntax-ppss)))
6417 ((nth 3 state) ;Inside string
6419 ((nth 7 state) ;Inside // comment
6423 ((nth 4 state) ;Inside /* comment
6424 (search-forward "*/")
6426 ((verilog-in-attribute-p) ;Inside (* attribute
6427 (search-forward "*)" nil t)
6430 (skip-chars-forward " \t\n\f")
6433 ((looking-at "\\/\\*")
6436 (goto-char (match-end 0))
6437 (if (search-forward "*/" nil t)
6439 (skip-chars-forward " \t\n\f")
6444 ((and (looking-at "(\\*") ; attribute start, but not an event (*) or (* )
6445 (not (looking-at "(\\*\\s-*)")))
6448 (goto-char (match-end 0))
6449 (if (search-forward "*)" nil t)
6451 (skip-chars-forward " \t\n\f")
6459 (defun verilog-indent-line-relative ()
6460 "Cheap version of indent line.
6461 Only look at a few lines to determine indent level."
6465 (if (looking-at "^[ \t]*$")
6466 (cond ;- A blank line; No need to be too smart.
6468 (setq indent-str (list 'cpp 0)))
6469 ((verilog-continued-line)
6470 (let ((sp1 (point)))
6471 (if (verilog-continued-line)
6475 (list 'statement (verilog-current-indent-level))))
6477 (setq indent-str (list 'block (verilog-current-indent-level)))))
6480 (setq indent-str (verilog-calculate-indent))))
6481 (progn (skip-chars-forward " \t")
6482 (setq indent-str (verilog-calculate-indent))))
6483 (verilog-do-indent indent-str)))
6485 (defun verilog-indent-line ()
6486 "Indent for special part of code."
6487 (verilog-do-indent (verilog-calculate-indent)))
6489 (defun verilog-do-indent (indent-str)
6490 (let ((type (car indent-str))
6491 (ind (car (cdr indent-str))))
6493 (; handle continued exp
6495 (let ((here (point)))
6496 (verilog-backward-syntactic-ws)
6499 (= (preceding-char) ?\,)
6501 (verilog-beg-of-statement-1)
6502 (looking-at verilog-declaration-re)))
6507 (verilog-beg-of-statement-1)
6509 (if (looking-at verilog-declaration-re)
6510 (progn ; we have multiple words
6511 (goto-char (match-end 0))
6512 (skip-chars-forward " \t")
6514 ((and verilog-indent-declaration-macros
6515 (= (following-char) ?\`))
6519 (skip-chars-forward " \t")))
6520 ((= (following-char) ?\[)
6523 (verilog-backward-up-list -1)
6524 (skip-chars-forward " \t"))))
6528 (+ (current-column) verilog-cexp-indent))))))
6530 (indent-line-to val)
6531 (if (and (not verilog-indent-lists)
6533 (verilog-pretty-declarations-auto))
6535 ((= (preceding-char) ?\) )
6537 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
6538 (indent-line-to val)))
6542 (verilog-beg-of-statement-1)
6543 (if (and (< (point) here)
6544 (verilog-re-search-forward "=[ \\t]*" here 'move)
6545 ;; not at a |=>, #=#, or [=n] operator
6546 (not (string-match "\\[=.\\|#=#\\||=>"
6547 (or (buffer-substring (- (point) 2) (1+ (point)))
6548 "")))) ; don't let buffer over/under-run spoil the party
6549 (setq val (current-column))
6550 (setq val (eval (cdr (assoc type verilog-indent-alist)))))
6552 (indent-line-to val))))))
6554 (; handle inside parenthetical expressions
6555 (eq type 'cparenexp)
6557 (val (save-excursion
6558 (verilog-backward-up-list 1)
6560 (if verilog-indent-lists
6561 (skip-chars-forward " \t")
6562 (verilog-forward-syntactic-ws))
6566 (decl (save-excursion
6568 (verilog-forward-syntactic-ws)
6570 (looking-at verilog-declaration-re))))
6571 (indent-line-to val)
6573 (verilog-pretty-declarations-auto))))
6575 (;-- Handle the ends
6577 (looking-at verilog-end-block-re)
6578 (verilog-at-close-constraint-p)
6579 (verilog-at-close-struct-p))
6580 (let ((val (if (eq type 'statement)
6581 (- ind verilog-indent-level)
6583 (indent-line-to val)))
6585 (;-- Case -- maybe line 'em up
6586 (and (eq type 'case) (not (looking-at "^[ \t]*$")))
6589 ((looking-at "\\<endcase\\>")
6590 (indent-line-to ind))
6592 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
6593 (indent-line-to val))))))
6596 (and (eq type 'defun)
6597 (looking-at verilog-zero-indent-re))
6604 (looking-at verilog-declaration-re)
6605 ;; Do not consider "virtual function", "virtual task", "virtual class"
6607 (not (looking-at (concat verilog-declaration-re
6608 "\\s-+\\(function\\|task\\|class\\)\\b"))))
6609 (verilog-indent-declaration ind))
6611 (;-- form feeds - ignored as bug in indent-line-to in < 24.5
6614 (;-- Everything else
6616 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
6617 (indent-line-to val))))
6619 (if (looking-at "[ \t]+$")
6620 (skip-chars-forward " \t"))
6621 indent-str ; Return indent data
6624 (defun verilog-current-indent-level ()
6625 "Return the indent-level of the current statement."
6629 (setq par-pos (verilog-parenthesis-depth))
6633 (setq par-pos (verilog-parenthesis-depth)))
6634 (skip-chars-forward " \t")
6637 (defun verilog-case-indent-level ()
6638 "Return the indent-level of the current statement.
6639 Do not count named blocks or case-statements."
6641 (skip-chars-forward " \t")
6643 ((looking-at verilog-named-block-re)
6645 ((and (not (looking-at verilog-extended-case-re))
6646 (looking-at "^[^:;]+[ \t]*:"))
6647 (verilog-re-search-forward ":" nil t)
6648 (skip-chars-forward " \t")
6651 (current-column)))))
6653 (defun verilog-indent-comment ()
6654 "Indent current line as comment."
6657 ((verilog-in-star-comment-p)
6659 (re-search-backward "/\\*" nil t)
6660 (1+(current-column))))
6665 (re-search-backward "//" nil t)
6666 (current-column))))))
6667 (indent-line-to stcol)
6670 (defun verilog-more-comment ()
6671 "Make more comment lines like the previous."
6675 ((verilog-in-star-comment-p)
6678 (re-search-backward "/\\*" nil t)
6679 (1+(current-column))))
6684 (re-search-backward "//" nil t)
6685 (current-column))))))
6691 (skip-chars-forward " \t")
6692 (looking-at "\\*")))
6695 (defun verilog-comment-indent (&optional _arg)
6696 "Return the column number the line should be indented to.
6697 _ARG is ignored, for `comment-indent-function' compatibility."
6699 ((verilog-in-star-comment-p)
6701 (re-search-backward "/\\*" nil t)
6702 (1+(current-column))))
6707 (re-search-backward "//" nil t)
6708 (current-column)))))
6712 (defun verilog-pretty-declarations-auto (&optional quiet)
6713 "Call `verilog-pretty-declarations' QUIET based on `verilog-auto-lineup'."
6714 (when (or (eq 'all verilog-auto-lineup)
6715 (eq 'declarations verilog-auto-lineup))
6716 (verilog-pretty-declarations quiet)))
6718 (defun verilog-pretty-declarations (&optional quiet)
6719 "Line up declarations around point.
6720 Be verbose about progress unless optional QUIET set."
6722 (let* ((m1 (make-marker))
6736 ;; (verilog-beg-of-statement-1)
6738 (verilog-forward-syntactic-ws)
6739 (and (not (verilog-in-directive-p)) ; could have `define input foo
6740 (looking-at verilog-declaration-re)))
6742 (if (verilog-parenthesis-depth)
6743 ;; in an argument list or parameter block
6744 (setq el (verilog-backward-up-list -1)
6747 (verilog-backward-up-list 1)
6748 (forward-line) ; ignore ( input foo,
6749 (verilog-re-search-forward verilog-declaration-re el 'move)
6750 (goto-char (match-beginning 0))
6751 (skip-chars-backward " \t")
6753 startpos (set-marker (make-marker) start)
6756 (verilog-backward-up-list -1)
6758 (verilog-backward-syntactic-ws)
6760 endpos (set-marker (make-marker) end)
6764 (skip-chars-forward " \t")
6766 ;; in a declaration block (not in argument list)
6769 (verilog-beg-of-statement-1)
6770 (while (and (looking-at verilog-declaration-re)
6772 (skip-chars-backward " \t")
6775 (verilog-backward-syntactic-ws)
6777 (verilog-beg-of-statement-1))
6779 startpos (set-marker (make-marker) start)
6782 (verilog-end-of-statement)
6783 (setq e (point)) ;Might be on last line
6784 (verilog-forward-syntactic-ws)
6785 (while (looking-at verilog-declaration-re)
6786 (verilog-end-of-statement)
6788 (verilog-forward-syntactic-ws))
6790 endpos (set-marker (make-marker) end)
6793 (verilog-do-indent (verilog-calculate-indent))
6794 (verilog-forward-ws&directives)
6796 ;; OK, start and end are set
6797 (goto-char (marker-position startpos))
6798 (if (and (not quiet)
6799 (> (- end start) 100))
6800 (message "Lining up declarations..(please stand by)"))
6801 ;; Get the beginning of line indent first
6802 (while (progn (setq e (marker-position endpos))
6805 ((save-excursion (skip-chars-backward " \t")
6807 (verilog-forward-ws&directives)
6808 (indent-line-to base-ind)
6809 (verilog-forward-ws&directives)
6811 (verilog-re-search-forward "[ \t\n\f]" e 'move)))
6814 (verilog-re-search-forward "[ \t\n\f]" e 'move)))
6817 ;; Now find biggest prefix
6818 (setq ind (verilog-get-lineup-indent (marker-position startpos) endpos))
6819 ;; Now indent each line.
6820 (goto-char (marker-position startpos))
6821 (while (progn (setq e (marker-position endpos))
6822 (setq r (- e (point)))
6825 (unless quiet (message "%d" r))
6826 ;; (verilog-do-indent (verilog-calculate-indent)))
6827 (verilog-forward-ws&directives)
6829 ((or (and verilog-indent-declaration-macros
6830 (looking-at verilog-declaration-re-2-macro))
6831 (looking-at verilog-declaration-re-2-no-macro))
6832 (let ((p (match-end 0)))
6834 (if (verilog-re-search-forward "[[#`]" p 'move)
6838 (goto-char (marker-position m1))
6844 ((verilog-continued-line-1 (marker-position startpos))
6846 (indent-line-to ind))
6847 ((verilog-in-struct-p)
6848 ;; could have a declaration of a user defined item
6850 (verilog-end-of-statement))
6851 (t ; Must be comment or white space
6853 (verilog-forward-ws&directives)
6856 (unless quiet (message "")))))))
6858 (defun verilog-pretty-expr (&optional quiet _myre)
6859 "Line up expressions around point, optionally QUIET with regexp _MYRE ignored."
6861 (if (not (verilog-in-comment-or-string-p))
6863 (let ( (rexp (concat "^\\s-*" verilog-complete-reg))
6864 (rexp1 (concat "^\\s-*" verilog-basic-complete-re)))
6866 (if (and (not (looking-at rexp ))
6867 (looking-at verilog-assignment-operation-re)
6869 (goto-char (match-end 2))
6870 (and (not (verilog-in-attribute-p))
6871 (not (verilog-in-parameter-p))
6872 (not (verilog-in-comment-or-string-p)))))
6873 (let* ((here (point))
6879 (verilog-backward-syntactic-ws)
6881 (while (and (not (looking-at rexp1))
6882 (looking-at verilog-assignment-operation-re)
6886 (verilog-backward-syntactic-ws)
6888 ) ;Ack, need to grok `define
6894 (setq e (point)) ;Might be on last line
6895 (verilog-forward-syntactic-ws)
6898 (not (looking-at rexp1 ))
6899 (looking-at verilog-assignment-operation-re)
6902 (not (eq e (point)))))
6904 (verilog-forward-syntactic-ws)
6908 (endpos (set-marker (make-marker) end))
6912 (verilog-do-indent (verilog-calculate-indent))
6913 (if (and (not quiet)
6914 (> (- end start) 100))
6915 (message "Lining up expressions..(please stand by)"))
6917 ;; Set indent to minimum throughout region
6918 (while (< (point) (marker-position endpos))
6920 (verilog-just-one-space verilog-assignment-operation-re)
6922 (verilog-do-indent (verilog-calculate-indent))
6924 (verilog-forward-syntactic-ws)
6927 ;; Now find biggest prefix
6928 (setq ind (verilog-get-lineup-indent-2 verilog-assignment-operation-re start endpos))
6930 ;; Now indent each line.
6932 (while (progn (setq e (marker-position endpos))
6933 (setq r (- e (point)))
6936 (if (not quiet) (message "%d" r))
6938 ((looking-at verilog-assignment-operation-re)
6939 (goto-char (match-beginning 2))
6940 (if (not (or (verilog-in-parenthesis-p) ; leave attributes and comparisons alone
6941 (verilog-in-coverage-p)))
6942 (if (eq (char-after) ?=)
6943 (indent-to (1+ ind)) ; line up the = of the <= with surrounding =
6947 ((verilog-continued-line-1 start)
6949 (indent-line-to ind))
6950 (t ; Must be comment or white space
6952 (verilog-forward-ws&directives)
6956 (unless quiet (message ""))
6959 (defun verilog-just-one-space (myre)
6960 "Remove extra spaces around regular expression MYRE."
6962 (if (and (not(looking-at verilog-complete-reg))
6964 (let ((p1 (match-end 1))
6970 (just-one-space)))))
6972 (defun verilog-indent-declaration (baseind)
6973 "Indent current lines as declaration.
6974 Line up the variable names based on previous declaration's indentation.
6975 BASEIND is the base indent to offset everything."
6977 (let ((pos (point-marker))
6978 (lim (save-excursion
6979 ;; (verilog-re-search-backward verilog-declaration-opener nil 'move)
6980 (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)\\|\\(\\<task\\>\\)" nil 'move)
6986 (+ baseind (eval (cdr (assoc 'declaration verilog-indent-alist)))))
6987 (indent-line-to val)
6989 ;; Use previous declaration (in this module) as template.
6990 (if (or (eq 'all verilog-auto-lineup)
6991 (eq 'declarations verilog-auto-lineup))
6992 (if (verilog-re-search-backward
6993 (or (and verilog-indent-declaration-macros
6994 verilog-declaration-re-1-macro)
6995 verilog-declaration-re-1-no-macro) lim t)
6997 (goto-char (match-end 0))
6998 (skip-chars-forward " \t")
6999 (setq ind (current-column))
7003 (eval (cdr (assoc 'declaration verilog-indent-alist)))))
7004 (indent-line-to val)
7005 (if (and verilog-indent-declaration-macros
7006 (looking-at verilog-declaration-re-2-macro))
7007 (let ((p (match-end 0)))
7009 (if (verilog-re-search-forward "[[#`]" p 'move)
7013 (goto-char (marker-position m1))
7016 (if (/= (current-column) ind)
7020 (if (looking-at verilog-declaration-re-2-no-macro)
7021 (let ((p (match-end 0)))
7023 (if (verilog-re-search-forward "[[`#]" p 'move)
7027 (goto-char (marker-position m1))
7030 (if (/= (current-column) ind)
7033 (indent-to ind))))))))))
7036 (defun verilog-get-lineup-indent (b edpos)
7037 "Return the indent level that will line up several lines within the region.
7038 Region is defined by B and EDPOS."
7042 ;; Get rightmost position
7043 (while (progn (setq e (marker-position edpos))
7045 (if (verilog-re-search-forward
7046 (or (and verilog-indent-declaration-macros
7047 verilog-declaration-re-1-macro)
7048 verilog-declaration-re-1-no-macro) e 'move)
7050 (goto-char (match-end 0))
7051 (verilog-backward-syntactic-ws)
7052 (if (> (current-column) ind)
7053 (setq ind (current-column)))
7054 (goto-char (match-end 0)))))
7057 ;; No lineup-string found
7060 (verilog-backward-syntactic-ws)
7061 ;;(skip-chars-backward " \t")
7062 (1+ (current-column))))))
7064 (defun verilog-get-lineup-indent-2 (myre b edpos)
7065 "Return the indent level that will line up several lines within the region."
7069 ;; Get rightmost position
7070 (while (progn (setq e (marker-position edpos))
7072 (if (and (verilog-re-search-forward myre e 'move)
7073 (not (verilog-in-attribute-p))) ; skip attribute exprs
7075 (goto-char (match-beginning 2))
7076 (verilog-backward-syntactic-ws)
7077 (if (> (current-column) ind)
7078 (setq ind (current-column)))
7079 (goto-char (match-end 0)))
7083 ;; No lineup-string found
7086 (skip-chars-backward " \t")
7087 (1+ (current-column))))))
7089 (defun verilog-comment-depth (type val)
7090 "A useful mode debugging aide. TYPE and VAL are comments for insertion."
7097 (if (re-search-backward " /\\* [#-]# [a-zA-Z]+ [0-9]+ ## \\*/" b t)
7099 (replace-match " /* -# ## */")
7103 (insert " /* ## ## */"))))
7106 (format "%s %d" type val))))
7111 (defvar verilog-str nil)
7112 (defvar verilog-all nil)
7113 (defvar verilog-pred nil)
7114 (defvar verilog-buffer-to-use nil)
7115 (defvar verilog-flag nil)
7116 (defvar verilog-toggle-completions nil
7117 "True means \\<verilog-mode-map>\\[verilog-complete-word] should try all possible completions one by one.
7118 Repeated use of \\[verilog-complete-word] will show you all of them.
7119 Normally, when there is more than one possible completion,
7120 it displays a list of all possible completions.")
7123 (defvar verilog-type-keywords
7125 "and" "buf" "bufif0" "bufif1" "cmos" "defparam" "inout" "input"
7126 "integer" "localparam" "logic" "mailbox" "nand" "nmos" "nor" "not" "notif0"
7127 "notif1" "or" "output" "parameter" "pmos" "pull0" "pull1" "pulldown" "pullup"
7128 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran" "rtranif0"
7129 "rtranif1" "semaphore" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1"
7130 "triand" "trior" "trireg" "wand" "wire" "wor" "xnor" "xor"
7132 "Keywords for types used when completing a word in a declaration or parmlist.
7133 \(integer, real, reg...)")
7135 (defvar verilog-cpp-keywords
7136 '("module" "macromodule" "primitive" "timescale" "define" "ifdef" "ifndef" "else"
7138 "Keywords to complete when at first word of a line in declarative scope.
7139 \(initial, always, begin, assign...)
7140 The procedures and variables defined within the Verilog program
7141 will be completed at runtime and should not be added to this list.")
7143 (defvar verilog-defun-keywords
7146 "always" "always_comb" "always_ff" "always_latch" "assign"
7147 "begin" "end" "generate" "endgenerate" "module" "endmodule"
7148 "specify" "endspecify" "function" "endfunction" "initial" "final"
7149 "task" "endtask" "primitive" "endprimitive"
7151 verilog-type-keywords)
7152 "Keywords to complete when at first word of a line in declarative scope.
7153 \(initial, always, begin, assign...)
7154 The procedures and variables defined within the Verilog program
7155 will be completed at runtime and should not be added to this list.")
7157 (defvar verilog-block-keywords
7159 "begin" "break" "case" "continue" "else" "end" "endfunction"
7160 "endgenerate" "endinterface" "endpackage" "endspecify" "endtask"
7161 "for" "fork" "if" "join" "join_any" "join_none" "repeat" "return"
7163 "Keywords to complete when at first word of a line in behavioral scope.
7164 \(begin, if, then, else, for, fork...)
7165 The procedures and variables defined within the Verilog program
7166 will be completed at runtime and should not be added to this list.")
7168 (defvar verilog-tf-keywords
7169 '("begin" "break" "fork" "join" "join_any" "join_none" "case" "end" "endtask" "endfunction" "if" "else" "for" "while" "repeat")
7170 "Keywords to complete when at first word of a line in a task or function.
7171 \(begin, if, then, else, for, fork.)
7172 The procedures and variables defined within the Verilog program
7173 will be completed at runtime and should not be added to this list.")
7175 (defvar verilog-case-keywords
7176 '("begin" "fork" "join" "join_any" "join_none" "case" "end" "endcase" "if" "else" "for" "repeat")
7177 "Keywords to complete when at first word of a line in case scope.
7178 \(begin, if, then, else, for, fork...)
7179 The procedures and variables defined within the Verilog program
7180 will be completed at runtime and should not be added to this list.")
7182 (defvar verilog-separator-keywords
7183 '("else" "then" "begin")
7184 "Keywords to complete when NOT standing at the first word of a statement.
7185 \(else, then, begin...)
7186 Variables and function names defined within the Verilog program
7187 will be completed at runtime and should not be added to this list.")
7189 (defvar verilog-gate-ios
7190 ;; All these have an implied {"input"...} at the end
7204 ("pulldown" "output")
7209 ("rtran" "inout" "inout")
7210 ("rtranif0" "inout" "inout")
7211 ("rtranif1" "inout" "inout")
7212 ("tran" "inout" "inout")
7213 ("tranif0" "inout" "inout")
7214 ("tranif1" "inout" "inout")
7217 "Map of direction for each positional argument to each gate primitive.")
7219 (defvar verilog-gate-keywords (mapcar `car verilog-gate-ios)
7220 "Keywords for gate primitives.")
7222 (defun verilog-string-diff (str1 str2)
7223 "Return index of first letter where STR1 and STR2 differs."
7227 (if (or (> (1+ diff) (length str1))
7228 (> (1+ diff) (length str2)))
7230 (or (equal (aref str1 diff) (aref str2 diff))
7232 (setq diff (1+ diff))))))
7234 ;; Calculate all possible completions for functions if argument is `function',
7235 ;; completions for procedures if argument is `procedure' or both functions and
7236 ;; procedures otherwise.
7238 (defun verilog-func-completion (type)
7239 "Build regular expression for module/task/function names.
7240 TYPE is `module', `tf' for task or function, or t if unknown."
7241 (if (string= verilog-str "")
7242 (setq verilog-str "[a-zA-Z_]"))
7243 (let ((verilog-str (concat (cond
7244 ((eq type 'module) "\\<\\(module\\)\\s +")
7245 ((eq type 'tf) "\\<\\(task\\|function\\)\\s +")
7246 (t "\\<\\(task\\|function\\|module\\)\\s +"))
7247 "\\<\\(" verilog-str "[a-zA-Z0-9_.]*\\)\\>"))
7250 (if (not (looking-at verilog-defun-re))
7251 (verilog-re-search-backward verilog-defun-re nil t))
7254 ;; Search through all reachable functions
7255 (goto-char (point-min))
7256 (while (verilog-re-search-forward verilog-str (point-max) t)
7257 (progn (setq match (buffer-substring (match-beginning 2)
7259 (if (or (null verilog-pred)
7260 (funcall verilog-pred match))
7261 (setq verilog-all (cons match verilog-all)))))
7262 (if (match-beginning 0)
7263 (goto-char (match-beginning 0)))))
7265 (defun verilog-get-completion-decl (end)
7266 "Macro for searching through current declaration (var, type or const)
7267 for matches of `str' and adding the occurrence tp `all' through point END."
7268 (let ((re (or (and verilog-indent-declaration-macros
7269 verilog-declaration-re-2-macro)
7270 verilog-declaration-re-2-no-macro))
7273 (while (and (< (point) end)
7274 (verilog-re-search-forward re end t))
7275 ;; Traverse current line
7276 (setq decl-end (save-excursion (verilog-declaration-end)))
7277 (while (and (verilog-re-search-forward verilog-symbol-re decl-end t)
7278 (not (match-end 1)))
7279 (setq match (buffer-substring (match-beginning 0) (match-end 0)))
7280 (if (string-match (concat "\\<" verilog-str) match)
7281 (if (or (null verilog-pred)
7282 (funcall verilog-pred match))
7283 (setq verilog-all (cons match verilog-all)))))
7287 (defun verilog-var-completion ()
7288 "Calculate all possible completions for variables (or constants)."
7289 (let ((start (point)))
7290 ;; Search for all reachable var declarations
7291 (verilog-beg-of-defun)
7293 ;; Check var declarations
7294 (verilog-get-completion-decl start))))
7296 (defun verilog-keyword-completion (keyword-list)
7297 "Give list of all possible completions of keywords in KEYWORD-LIST."
7299 (if (string-match (concat "\\<" verilog-str) s)
7300 (if (or (null verilog-pred)
7301 (funcall verilog-pred s))
7302 (setq verilog-all (cons s verilog-all)))))
7306 (defun verilog-completion (verilog-str verilog-pred verilog-flag)
7307 "Function passed to `completing-read', `try-completion' or `all-completions'.
7308 Called to get completion on VERILOG-STR. If VERILOG-PRED is non-nil, it
7309 must be a function to be called for every match to check if this should
7310 really be a match. If VERILOG-FLAG is t, the function returns a list of
7311 all possible completions. If VERILOG-FLAG is nil it returns a string,
7312 the longest possible completion, or t if VERILOG-STR is an exact match.
7313 If VERILOG-FLAG is `lambda', the function returns t if VERILOG-STR is an
7314 exact match, nil otherwise."
7316 (let ((verilog-all nil))
7317 ;; Set buffer to use for searching labels. This should be set
7318 ;; within functions which use verilog-completions
7319 (set-buffer verilog-buffer-to-use)
7321 ;; Determine what should be completed
7322 (let ((state (car (verilog-calculate-indent))))
7323 (cond ((eq state 'defun)
7324 (save-excursion (verilog-var-completion))
7325 (verilog-func-completion 'module)
7326 (verilog-keyword-completion verilog-defun-keywords))
7328 ((eq state 'behavioral)
7329 (save-excursion (verilog-var-completion))
7330 (verilog-func-completion 'module)
7331 (verilog-keyword-completion verilog-defun-keywords))
7334 (save-excursion (verilog-var-completion))
7335 (verilog-func-completion 'tf)
7336 (verilog-keyword-completion verilog-block-keywords))
7339 (save-excursion (verilog-var-completion))
7340 (verilog-func-completion 'tf)
7341 (verilog-keyword-completion verilog-case-keywords))
7344 (save-excursion (verilog-var-completion))
7345 (verilog-func-completion 'tf)
7346 (verilog-keyword-completion verilog-tf-keywords))
7349 (save-excursion (verilog-var-completion))
7350 (verilog-keyword-completion verilog-cpp-keywords))
7352 ((eq state 'cparenexp)
7353 (save-excursion (verilog-var-completion)))
7356 (save-excursion (verilog-var-completion))
7357 (verilog-func-completion 'both)
7358 (verilog-keyword-completion verilog-separator-keywords))))
7360 ;; Now we have built a list of all matches. Give response to caller
7361 (verilog-completion-response))))
7363 (defun verilog-completion-response ()
7364 (cond ((or (equal verilog-flag 'lambda) (null verilog-flag))
7365 ;; This was not called by all-completions
7366 (if (null verilog-all)
7367 ;; Return nil if there was no matching label
7369 ;; Get longest string common in the labels
7370 ;; FIXME: Why not use `try-completion'?
7371 (let* ((elm (cdr verilog-all))
7372 (match (car verilog-all))
7373 (min (length match))
7375 (if (string= match verilog-str)
7376 ;; Return t if first match was an exact match
7378 (while (not (null elm))
7379 ;; Find longest common string
7380 (if (< (setq tmp (verilog-string-diff match (car elm))) min)
7383 (setq match (substring match 0 min))))
7384 ;; Terminate with match=t if this is an exact match
7385 (if (string= (car elm) verilog-str)
7389 (setq elm (cdr elm)))))
7390 ;; If this is a test just for exact match, return nil ot t
7391 (if (and (equal verilog-flag 'lambda) (not (equal match 't)))
7394 ;; If flag is t, this was called by all-completions. Return
7395 ;; list of all possible completions
7399 (defvar verilog-last-word-numb 0)
7400 (defvar verilog-last-word-shown nil)
7401 (defvar verilog-last-completions nil)
7403 (defun verilog-complete-word ()
7404 "Complete word at current point.
7405 \(See also `verilog-toggle-completions', `verilog-type-keywords',
7406 and `verilog-separator-keywords'.)"
7407 ;; FIXME: Provide completion-at-point-function.
7409 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
7410 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
7411 (verilog-str (buffer-substring b e))
7412 ;; The following variable is used in verilog-completion
7413 (verilog-buffer-to-use (current-buffer))
7414 (allcomp (if (and verilog-toggle-completions
7415 (string= verilog-last-word-shown verilog-str))
7416 verilog-last-completions
7417 (all-completions verilog-str 'verilog-completion)))
7418 (match (if verilog-toggle-completions
7420 verilog-str (mapcar (lambda (elm)
7421 (cons elm 0)) allcomp)))))
7422 ;; Delete old string
7425 ;; Toggle-completions inserts whole labels
7426 (if verilog-toggle-completions
7428 ;; Update entry number in list
7429 (setq verilog-last-completions allcomp
7430 verilog-last-word-numb
7431 (if (>= verilog-last-word-numb (1- (length allcomp)))
7433 (1+ verilog-last-word-numb)))
7434 (setq verilog-last-word-shown (elt allcomp verilog-last-word-numb))
7435 ;; Display next match or same string if no match was found
7436 (if (not (null allcomp))
7437 (insert "" verilog-last-word-shown)
7438 (insert "" verilog-str)
7439 (message "(No match)")))
7440 ;; The other form of completion does not necessarily do that.
7442 ;; Insert match if found, or the original string if no match
7443 (if (or (null match) (equal match 't))
7444 (progn (insert "" verilog-str)
7445 (message "(No match)"))
7447 ;; Give message about current status of completion
7448 (cond ((equal match 't)
7449 (if (not (null (cdr allcomp)))
7450 (message "(Complete but not unique)")
7451 (message "(Sole completion)")))
7452 ;; Display buffer if the current completion didn't help
7453 ;; on completing the label.
7454 ((and (not (null (cdr allcomp))) (= (length verilog-str)
7456 (with-output-to-temp-buffer "*Completions*"
7457 (display-completion-list allcomp))
7458 ;; Wait for a key press. Then delete *Completion* window
7459 (momentary-string-display "" (point))
7460 (delete-window (get-buffer-window (get-buffer "*Completions*")))
7463 (defun verilog-show-completions ()
7464 "Show all possible completions at current point."
7466 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
7467 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
7468 (verilog-str (buffer-substring b e))
7469 ;; The following variable is used in verilog-completion
7470 (verilog-buffer-to-use (current-buffer))
7471 (allcomp (if (and verilog-toggle-completions
7472 (string= verilog-last-word-shown verilog-str))
7473 verilog-last-completions
7474 (all-completions verilog-str 'verilog-completion))))
7475 ;; Show possible completions in a temporary buffer.
7476 (with-output-to-temp-buffer "*Completions*"
7477 (display-completion-list allcomp))
7478 ;; Wait for a key press. Then delete *Completion* window
7479 (momentary-string-display "" (point))
7480 (delete-window (get-buffer-window (get-buffer "*Completions*")))))
7483 (defun verilog-get-default-symbol ()
7484 "Return symbol around current point as a string."
7486 (buffer-substring (progn
7487 (skip-chars-backward " \t")
7488 (skip-chars-backward "a-zA-Z0-9_")
7491 (skip-chars-forward "a-zA-Z0-9_")
7494 (defun verilog-build-defun-re (str &optional arg)
7495 "Return function/task/module starting with STR as regular expression.
7496 With optional second ARG non-nil, STR is the complete name of the instruction."
7498 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "\\)\\>")
7499 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "[a-zA-Z0-9_]*\\)\\>")))
7501 (defun verilog-comp-defun (verilog-str verilog-pred verilog-flag)
7502 "Function passed to `completing-read', `try-completion' or `all-completions'.
7503 Returns a completion on any function name based on VERILOG-STR prefix. If
7504 VERILOG-PRED is non-nil, it must be a function to be called for every match
7505 to check if this should really be a match. If VERILOG-FLAG is t, the
7506 function returns a list of all possible completions. If it is nil it
7507 returns a string, the longest possible completion, or t if VERILOG-STR is
7508 an exact match. If VERILOG-FLAG is `lambda', the function returns t if
7509 VERILOG-STR is an exact match, nil otherwise."
7511 (let ((verilog-all nil)
7514 ;; Set buffer to use for searching labels. This should be set
7515 ;; within functions which use verilog-completions
7516 (set-buffer verilog-buffer-to-use)
7518 (let ((verilog-str verilog-str))
7519 ;; Build regular expression for functions
7520 (if (string= verilog-str "")
7521 (setq verilog-str (verilog-build-defun-re "[a-zA-Z_]"))
7522 (setq verilog-str (verilog-build-defun-re verilog-str)))
7523 (goto-char (point-min))
7525 ;; Build a list of all possible completions
7526 (while (verilog-re-search-forward verilog-str nil t)
7527 (setq match (buffer-substring (match-beginning 2) (match-end 2)))
7528 (if (or (null verilog-pred)
7529 (funcall verilog-pred match))
7530 (setq verilog-all (cons match verilog-all)))))
7532 ;; Now we have built a list of all matches. Give response to caller
7533 (verilog-completion-response))))
7535 (defun verilog-goto-defun ()
7536 "Move to specified Verilog module/interface/task/function.
7537 The default is a name found in the buffer around point.
7538 If search fails, other files are checked based on
7539 `verilog-library-flags'."
7541 (let* ((default (verilog-get-default-symbol))
7542 ;; The following variable is used in verilog-comp-function
7543 (verilog-buffer-to-use (current-buffer))
7544 (label (if (not (string= default ""))
7545 ;; Do completion with default
7546 (completing-read (concat "Goto-Label: (default "
7548 'verilog-comp-defun nil nil "")
7549 ;; There is no default value. Complete without it
7550 (completing-read "Goto-Label: "
7551 'verilog-comp-defun nil nil "")))
7553 ;; Make sure library paths are correct, in case need to resolve module
7554 (verilog-auto-reeval-locals)
7555 (verilog-getopt-flags)
7556 ;; If there was no response on prompt, use default value
7557 (if (string= label "")
7558 (setq label default))
7559 ;; Goto right place in buffer if label is not an empty string
7560 (or (string= label "")
7563 (goto-char (point-min))
7565 (re-search-forward (verilog-build-defun-re label t) nil t)))
7568 (beginning-of-line))
7570 (verilog-goto-defun-file label))))
7572 ;; Eliminate compile warning
7573 (defvar occur-pos-list)
7575 (defun verilog-showscopes ()
7576 "List all scopes in this module."
7578 (let ((buffer (current-buffer))
7582 (prevpos (point-min))
7583 (final-context-start (make-marker))
7584 (regexp "\\(module\\s-+\\w+\\s-*(\\)\\|\\(\\w+\\s-+\\w+\\s-*(\\)"))
7585 (with-output-to-temp-buffer "*Occur*"
7587 (message "Searching for %s ..." regexp)
7588 ;; Find next match, but give up if prev match was at end of buffer.
7589 (while (and (not (= prevpos (point-max)))
7590 (verilog-re-search-forward regexp nil t))
7591 (goto-char (match-beginning 0))
7594 (setq linenum (+ linenum (count-lines prevpos (point)))))
7595 (setq prevpos (point))
7596 (goto-char (match-end 0))
7597 (let* ((start (save-excursion
7598 (goto-char (match-beginning 0))
7599 (forward-line (if (< nlines 0) nlines (- nlines)))
7601 (end (save-excursion
7602 (goto-char (match-end 0))
7604 (forward-line (1+ nlines))
7607 (tag (format "%3d" linenum))
7608 (empty (make-string (length tag) ?\ ))
7611 (setq tem (make-marker))
7612 (set-marker tem (point))
7613 (set-buffer standard-output)
7614 (setq occur-pos-list (cons tem occur-pos-list))
7615 (or first (zerop nlines)
7616 (insert "--------\n"))
7618 (insert-buffer-substring buffer start end)
7619 (backward-char (- end start))
7620 (setq tem (if (< nlines 0) (- nlines) nlines))
7624 (setq tem (1- tem)))
7625 (let ((this-linenum linenum))
7626 (set-marker final-context-start
7627 (+ (point) (- (match-end 0) (match-beginning 0))))
7628 (while (< (point) final-context-start)
7630 (setq tag (format "%3d" this-linenum)))
7631 (insert tag ?:)))))))
7632 (set-buffer-modified-p nil))))
7635 ;; Highlight helper functions
7636 (defconst verilog-directive-regexp "\\(translate\\|coverage\\|lint\\)_")
7638 (defun verilog-within-translate-off ()
7639 "Return point if within translate-off region, else nil."
7640 (and (save-excursion
7642 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "\\(on\\|off\\)\\>")
7644 (equal "off" (match-string 2))
7647 (defun verilog-start-translate-off (limit)
7648 "Return point before translate-off directive if before LIMIT, else nil."
7649 (when (re-search-forward
7650 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
7652 (match-beginning 0)))
7654 (defun verilog-back-to-start-translate-off (limit)
7655 "Return point before translate-off directive if before LIMIT, else nil."
7656 (when (re-search-backward
7657 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
7659 (match-beginning 0)))
7661 (defun verilog-end-translate-off (limit)
7662 "Return point after translate-on directive if before LIMIT, else nil."
7664 (re-search-forward (concat
7665 "//\\s-*.*\\s-*" verilog-directive-regexp "on\\>") limit t))
7667 (defun verilog-match-translate-off (limit)
7668 "Match a translate-off block, setting `match-data' and returning t, else nil.
7669 Bound search by LIMIT."
7670 (when (< (point) limit)
7671 (let ((start (or (verilog-within-translate-off)
7672 (verilog-start-translate-off limit)))
7673 (case-fold-search t))
7675 (let ((end (or (verilog-end-translate-off limit) limit)))
7676 (set-match-data (list start end))
7677 (goto-char end))))))
7679 (defun verilog-font-lock-match-item (limit)
7680 "Match, and move over, any declaration item after point.
7681 Bound search by LIMIT. Adapted from
7682 `font-lock-match-c-style-declaration-item-and-skip-to-next'."
7685 (narrow-to-region (point-min) limit)
7687 (when (looking-at "\\s-*\\([a-zA-Z]\\w*\\)")
7689 (goto-char (match-end 1))
7690 ;; move to next item
7691 (if (looking-at "\\(\\s-*,\\)")
7692 (goto-char (match-end 1))
7697 ;; Added by Subbu Meiyappan for Header
7699 (defun verilog-header ()
7700 "Insert a standard Verilog file header.
7701 See also `verilog-sk-header' for an alternative format."
7703 (let ((start (point)))
7705 //-----------------------------------------------------------------------------
7707 // Project : <project>
7708 //-----------------------------------------------------------------------------
7709 // File : <filename>
7710 // Author : <author>
7711 // Created : <credate>
7712 // Last modified : <moddate>
7713 //-----------------------------------------------------------------------------
7716 //-----------------------------------------------------------------------------
7717 // Copyright (c) <copydate> by <company> This model is the confidential and
7718 // proprietary property of <company> and the possession or use of this
7719 // file requires a written license from <company>.
7720 //------------------------------------------------------------------------------
7721 // Modification history :
7723 //-----------------------------------------------------------------------------
7727 (search-forward "<filename>")
7728 (replace-match (buffer-name) t t)
7729 (search-forward "<author>") (replace-match "" t t)
7730 (insert (user-full-name))
7731 (insert " <" (user-login-name) "@" (system-name) ">")
7732 (search-forward "<credate>") (replace-match "" t t)
7733 (verilog-insert-date)
7734 (search-forward "<moddate>") (replace-match "" t t)
7735 (verilog-insert-date)
7736 (search-forward "<copydate>") (replace-match "" t t)
7737 (verilog-insert-year)
7738 (search-forward "<modhist>") (replace-match "" t t)
7739 (verilog-insert-date)
7740 (insert " : created")
7743 (setq string (read-string "title: "))
7744 (search-forward "<title>")
7745 (replace-match string t t)
7746 (setq string (read-string "project: " verilog-project))
7747 (setq verilog-project string)
7748 (search-forward "<project>")
7749 (replace-match string t t)
7750 (setq string (read-string "Company: " verilog-company))
7751 (setq verilog-company string)
7752 (search-forward "<company>")
7753 (replace-match string t t)
7754 (search-forward "<company>")
7755 (replace-match string t t)
7756 (search-forward "<company>")
7757 (replace-match string t t)
7758 (search-backward "<description>")
7759 (replace-match "" t t))))
7761 ;; verilog-header Uses the verilog-insert-date function
7763 (defun verilog-insert-date ()
7764 "Insert date from the system."
7766 (if verilog-date-scientific-format
7767 (insert (format-time-string "%Y/%m/%d"))
7768 (insert (format-time-string "%d.%m.%Y"))))
7770 (defun verilog-insert-year ()
7771 "Insert year from the system."
7773 (insert (format-time-string "%Y")))
7776 ;;; Signal list parsing:
7779 ;; Elements of a signal list
7780 ;; Unfortunately we use 'assoc' on this, so can't be a vector
7781 (defsubst verilog-sig-new (name bits comment mem enum signed type multidim modport)
7782 (list name bits comment mem enum signed type multidim modport))
7783 (defsubst verilog-sig-name (sig)
7785 (defsubst verilog-sig-bits (sig) ; First element of packed array (pre signal-name)
7787 (defsubst verilog-sig-comment (sig)
7789 (defsubst verilog-sig-memory (sig) ; Unpacked array (post signal-name)
7791 (defsubst verilog-sig-enum (sig)
7793 (defsubst verilog-sig-signed (sig)
7795 (defsubst verilog-sig-type (sig)
7797 (defsubst verilog-sig-type-set (sig type)
7798 (setcar (nthcdr 6 sig) type))
7799 (defsubst verilog-sig-multidim (sig) ; Second and additional elements of packed array
7801 (defsubst verilog-sig-multidim-string (sig)
7802 (if (verilog-sig-multidim sig)
7803 (let ((str "") (args (verilog-sig-multidim sig)))
7805 (setq str (concat str (car args)))
7806 (setq args (cdr args)))
7808 (defsubst verilog-sig-modport (sig)
7810 (defsubst verilog-sig-width (sig)
7811 (verilog-make-width-expression (verilog-sig-bits sig)))
7813 (defsubst verilog-alw-new (outputs-del outputs-imm temps inputs)
7814 (vector outputs-del outputs-imm temps inputs))
7815 (defsubst verilog-alw-get-outputs-delayed (sigs)
7817 (defsubst verilog-alw-get-outputs-immediate (sigs)
7819 (defsubst verilog-alw-get-temps (sigs)
7821 (defsubst verilog-alw-get-inputs (sigs)
7823 (defsubst verilog-alw-get-uses-delayed (sigs)
7826 (defsubst verilog-modport-new (name clockings decls)
7827 (list name clockings decls))
7828 (defsubst verilog-modport-name (sig)
7830 (defsubst verilog-modport-clockings (sig)
7831 (nth 1 sig)) ; Returns list of names
7832 (defsubst verilog-modport-clockings-add (sig val)
7833 (setcar (nthcdr 1 sig) (cons val (nth 1 sig))))
7834 (defsubst verilog-modport-decls (sig)
7835 (nth 2 sig)) ; Returns verilog-decls-* structure
7836 (defsubst verilog-modport-decls-set (sig val)
7837 (setcar (nthcdr 2 sig) val))
7839 (defsubst verilog-modi-new (name fob pt type)
7840 (vector name fob pt type))
7841 (defsubst verilog-modi-name (modi)
7843 (defsubst verilog-modi-file-or-buffer (modi)
7845 (defsubst verilog-modi-get-point (modi)
7847 (defsubst verilog-modi-get-type (modi) ; "module" or "interface"
7849 (defsubst verilog-modi-get-decls (modi)
7850 (verilog-modi-cache-results modi 'verilog-read-decls))
7851 (defsubst verilog-modi-get-sub-decls (modi)
7852 (verilog-modi-cache-results modi 'verilog-read-sub-decls))
7854 ;; Signal reading for given module
7855 ;; Note these all take modi's - as returned from verilog-modi-current
7856 (defsubst verilog-decls-new (out inout in vars modports assigns consts gparams interfaces)
7857 (vector out inout in vars modports assigns consts gparams interfaces))
7858 (defsubst verilog-decls-append (a b)
7859 (cond ((not a) b) ((not b) a)
7860 (t (vector (append (aref a 0) (aref b 0)) (append (aref a 1) (aref b 1))
7861 (append (aref a 2) (aref b 2)) (append (aref a 3) (aref b 3))
7862 (append (aref a 4) (aref b 4)) (append (aref a 5) (aref b 5))
7863 (append (aref a 6) (aref b 6)) (append (aref a 7) (aref b 7))
7864 (append (aref a 8) (aref b 8))))))
7865 (defsubst verilog-decls-get-outputs (decls)
7867 (defsubst verilog-decls-get-inouts (decls)
7869 (defsubst verilog-decls-get-inputs (decls)
7871 (defsubst verilog-decls-get-vars (decls)
7873 (defsubst verilog-decls-get-modports (decls) ; Also for clocking blocks; contains another verilog-decls struct
7874 (aref decls 4)) ; Returns verilog-modport* structure
7875 (defsubst verilog-decls-get-assigns (decls)
7877 (defsubst verilog-decls-get-consts (decls)
7879 (defsubst verilog-decls-get-gparams (decls)
7881 (defsubst verilog-decls-get-interfaces (decls)
7885 (defsubst verilog-subdecls-new (out inout in intf intfd)
7886 (vector out inout in intf intfd))
7887 (defsubst verilog-subdecls-get-outputs (subdecls)
7889 (defsubst verilog-subdecls-get-inouts (subdecls)
7891 (defsubst verilog-subdecls-get-inputs (subdecls)
7893 (defsubst verilog-subdecls-get-interfaces (subdecls)
7895 (defsubst verilog-subdecls-get-interfaced (subdecls)
7898 (defun verilog-signals-from-signame (signame-list)
7899 "Return signals in standard form from SIGNAME-LIST, a simple list of names."
7900 (mapcar (lambda (name) (verilog-sig-new name nil nil nil nil nil nil nil nil))
7903 (defun verilog-signals-in (in-list not-list)
7904 "Return list of signals in IN-LIST that are also in NOT-LIST.
7905 Also remove any duplicates in IN-LIST.
7906 Signals must be in standard (base vector) form."
7907 ;; This function is hot, so implemented as O(1)
7908 (cond ((eval-when-compile (fboundp 'make-hash-table))
7909 (let ((ht (make-hash-table :test 'equal :rehash-size 4.0))
7910 (ht-not (make-hash-table :test 'equal :rehash-size 4.0))
7913 (puthash (car (car not-list)) t ht-not)
7914 (setq not-list (cdr not-list)))
7916 (when (and (gethash (verilog-sig-name (car in-list)) ht-not)
7917 (not (gethash (verilog-sig-name (car in-list)) ht)))
7918 (setq out-list (cons (car in-list) out-list))
7919 (puthash (verilog-sig-name (car in-list)) t ht))
7920 (setq in-list (cdr in-list)))
7921 (nreverse out-list)))
7922 ;; Slower Fallback if no hash tables (pre Emacs 21.1/XEmacs 21.4)
7926 (if (and (assoc (verilog-sig-name (car in-list)) not-list)
7927 (not (assoc (verilog-sig-name (car in-list)) out-list)))
7928 (setq out-list (cons (car in-list) out-list)))
7929 (setq in-list (cdr in-list)))
7930 (nreverse out-list)))))
7931 ;;(verilog-signals-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("C" "")))
7933 (defun verilog-signals-not-in (in-list not-list)
7934 "Return list of signals in IN-LIST that aren't also in NOT-LIST.
7935 Also remove any duplicates in IN-LIST.
7936 Signals must be in standard (base vector) form."
7937 ;; This function is hot, so implemented as O(1)
7938 (cond ((eval-when-compile (fboundp 'make-hash-table))
7939 (let ((ht (make-hash-table :test 'equal :rehash-size 4.0))
7942 (puthash (car (car not-list)) t ht)
7943 (setq not-list (cdr not-list)))
7945 (when (not (gethash (verilog-sig-name (car in-list)) ht))
7946 (setq out-list (cons (car in-list) out-list))
7947 (puthash (verilog-sig-name (car in-list)) t ht))
7948 (setq in-list (cdr in-list)))
7949 (nreverse out-list)))
7950 ;; Slower Fallback if no hash tables (pre Emacs 21.1/XEmacs 21.4)
7954 (if (and (not (assoc (verilog-sig-name (car in-list)) not-list))
7955 (not (assoc (verilog-sig-name (car in-list)) out-list)))
7956 (setq out-list (cons (car in-list) out-list)))
7957 (setq in-list (cdr in-list)))
7958 (nreverse out-list)))))
7959 ;;(verilog-signals-not-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("EXT" "")))
7961 (defun verilog-signals-not-in-struct (in-list not-list)
7962 "Return list of signals in IN-LIST that aren't also in NOT-LIST.
7963 Also remove any duplicates in IN-LIST.
7964 Any structure in not-list will remove all members in in-list.
7965 Signals must be in standard (base vector) form."
7966 (cond ((eval-when-compile (fboundp 'make-hash-table))
7967 (let ((ht (make-hash-table :test 'equal :rehash-size 4.0))
7970 (puthash (car (car not-list)) t ht)
7971 (setq not-list (cdr not-list)))
7973 (setq nm (verilog-sig-name (car in-list)))
7974 (when (not (gethash nm ht))
7976 (while (string-match "^\\([^\\].*\\)\\.[^.]+$" nm)
7977 (setq nm (match-string 1 nm))
7978 (setq addit (and addit
7979 (not (gethash nm ht)))))
7981 (setq out-list (cons (car in-list) out-list))
7982 (puthash (verilog-sig-name (car in-list)) t ht)))
7983 (setq in-list (cdr in-list)))
7984 (nreverse out-list)))
7985 ;; Slower Fallback if no hash tables (pre Emacs 21.1/XEmacs 21.4)
7987 (let (out-list addit nm)
7989 (setq nm (verilog-sig-name (car in-list)))
7990 (when (and (not (assoc nm not-list))
7991 (not (assoc nm out-list)))
7993 (while (string-match "^\\([^\\].*\\)\\.[^.]+$" nm)
7994 (setq nm (match-string 1 nm))
7995 (setq addit (and addit
7996 (not (assoc nm not-list)))))
7998 (setq out-list (cons (car in-list) out-list))))
7999 (setq in-list (cdr in-list)))
8000 (nreverse out-list)))))
8001 ;;(verilog-signals-not-in-struct '(("A" "") ("B" "") ("DEL.SUB.A" "[2:3]")) '(("DEL.SUB" "") ("EXT" "")))
8003 (defun verilog-signals-memory (in-list)
8004 "Return list of signals in IN-LIST that are memorized (multidimensional)."
8007 (if (nth 3 (car in-list))
8008 (setq out-list (cons (car in-list) out-list)))
8009 (setq in-list (cdr in-list)))
8011 ;;(verilog-signals-memory '(("A" nil nil "[3:0]")) '(("B" nil nil nil)))
8013 (defun verilog-signals-sort-compare (a b)
8014 "Compare signal A and B for sorting."
8015 (string< (verilog-sig-name a) (verilog-sig-name b)))
8017 (defun verilog-signals-not-params (in-list)
8018 "Return list of signals in IN-LIST that aren't parameters or numeric constants."
8021 ;; Namespace intentionally short for AUTOs and compatibility
8022 (unless (boundp (intern (concat "vh-" (verilog-sig-name (car in-list)))))
8023 (setq out-list (cons (car in-list) out-list)))
8024 (setq in-list (cdr in-list)))
8025 (nreverse out-list)))
8027 (defun verilog-signals-with (func in-list)
8028 "Return list of signals where FUNC is true executed on each signal in IN-LIST."
8031 (when (funcall func (car in-list))
8032 (setq out-list (cons (car in-list) out-list)))
8033 (setq in-list (cdr in-list)))
8034 (nreverse out-list)))
8036 (defun verilog-signals-combine-bus (in-list)
8037 "Return a list of signals in IN-LIST, with buses combined.
8038 Duplicate signals are also removed. For example A[2] and A[1] become A[2:1]."
8042 sig highbit lowbit ; Temp information about current signal
8043 sv-name sv-highbit sv-lowbit ; Details about signal we are forming
8044 sv-comment sv-memory sv-enum sv-signed sv-type sv-multidim sv-busstring
8047 ;; Shove signals so duplicated signals will be adjacent
8048 (setq in-list (sort in-list `verilog-signals-sort-compare))
8050 (setq sig (car in-list))
8051 ;; No current signal; form from existing details
8053 (setq sv-name (verilog-sig-name sig)
8056 sv-comment (verilog-sig-comment sig)
8057 sv-memory (verilog-sig-memory sig)
8058 sv-enum (verilog-sig-enum sig)
8059 sv-signed (verilog-sig-signed sig)
8060 sv-type (verilog-sig-type sig)
8061 sv-multidim (verilog-sig-multidim sig)
8062 sv-modport (verilog-sig-modport sig)
8065 ;; Extract bus details
8066 (setq bus (verilog-sig-bits sig))
8067 (setq bus (and bus (verilog-simplify-range-expression bus)))
8069 (or (and (string-match "\\[\\([0-9]+\\):\\([0-9]+\\)\\]" bus)
8070 (setq highbit (string-to-number (match-string 1 bus))
8071 lowbit (string-to-number
8072 (match-string 2 bus))))
8073 (and (string-match "\\[\\([0-9]+\\)\\]" bus)
8074 (setq highbit (string-to-number (match-string 1 bus))
8076 ;; Combine bits in bus
8078 (setq sv-highbit (max highbit sv-highbit)
8079 sv-lowbit (min lowbit sv-lowbit))
8080 (setq sv-highbit highbit
8083 ;; String, probably something like `preproc:0
8084 (setq sv-busstring bus)))
8085 ;; Peek ahead to next signal
8086 (setq in-list (cdr in-list))
8087 (setq sig (car in-list))
8088 (cond ((and sig (equal sv-name (verilog-sig-name sig)))
8089 ;; Combine with this signal
8090 (when (and sv-busstring
8091 (not (equal sv-busstring (verilog-sig-bits sig))))
8092 (when nil ; Debugging
8093 (message (concat "Warning, can't merge into single bus `%s%s'"
8094 ", the AUTOs may be wrong")
8096 (setq buswarn ", Couldn't Merge"))
8097 (if (verilog-sig-comment sig) (setq combo ", ..."))
8098 (setq sv-memory (or sv-memory (verilog-sig-memory sig))
8099 sv-enum (or sv-enum (verilog-sig-enum sig))
8100 sv-signed (or sv-signed (verilog-sig-signed sig))
8101 sv-type (or sv-type (verilog-sig-type sig))
8102 sv-multidim (or sv-multidim (verilog-sig-multidim sig))
8103 sv-modport (or sv-modport (verilog-sig-modport sig))))
8104 ;; Doesn't match next signal, add to queue, zero in prep for next
8105 ;; Note sig may also be nil for the last signal in the list
8108 (cons (verilog-sig-new
8112 (concat "[" (int-to-string sv-highbit) ":"
8113 (int-to-string sv-lowbit) "]")))
8114 (concat sv-comment combo buswarn)
8115 sv-memory sv-enum sv-signed sv-type sv-multidim sv-modport)
8121 (defun verilog-sig-tieoff (sig)
8122 "Return tieoff expression for given SIG, with appropriate width.
8123 Tieoff value uses `verilog-active-low-regexp' and
8124 `verilog-auto-reset-widths'."
8126 (if (and verilog-active-low-regexp
8127 (verilog-string-match-fold verilog-active-low-regexp (verilog-sig-name sig)))
8129 (cond ((not verilog-auto-reset-widths)
8131 ((equal verilog-auto-reset-widths 'unbased)
8133 ;; Else presume verilog-auto-reset-widths is true
8135 (let* ((width (verilog-sig-width sig)))
8138 ((string-match "^[0-9]+$" width)
8139 (concat width (if (verilog-sig-signed sig) "'sh0" "'h0")))
8141 (concat "{" width "{1'b0}}"))))))))
8147 (defun verilog-decls-princ (decls &optional header prefix)
8148 "For debug, dump the `verilog-read-decls' structure DECLS.
8149 Use optional HEADER and PREFIX."
8151 (if header (princ header))
8152 (setq prefix (or prefix ""))
8153 (verilog-signals-princ (verilog-decls-get-outputs decls)
8154 (concat prefix "Outputs:\n") (concat prefix " "))
8155 (verilog-signals-princ (verilog-decls-get-inouts decls)
8156 (concat prefix "Inout:\n") (concat prefix " "))
8157 (verilog-signals-princ (verilog-decls-get-inputs decls)
8158 (concat prefix "Inputs:\n") (concat prefix " "))
8159 (verilog-signals-princ (verilog-decls-get-vars decls)
8160 (concat prefix "Vars:\n") (concat prefix " "))
8161 (verilog-signals-princ (verilog-decls-get-assigns decls)
8162 (concat prefix "Assigns:\n") (concat prefix " "))
8163 (verilog-signals-princ (verilog-decls-get-consts decls)
8164 (concat prefix "Consts:\n") (concat prefix " "))
8165 (verilog-signals-princ (verilog-decls-get-gparams decls)
8166 (concat prefix "Gparams:\n") (concat prefix " "))
8167 (verilog-signals-princ (verilog-decls-get-interfaces decls)
8168 (concat prefix "Interfaces:\n") (concat prefix " "))
8169 (verilog-modport-princ (verilog-decls-get-modports decls)
8170 (concat prefix "Modports:\n") (concat prefix " "))
8173 (defun verilog-signals-princ (signals &optional header prefix)
8174 "For debug, dump internal SIGNALS structures, with HEADER and PREFIX."
8176 (if header (princ header))
8178 (let ((sig (car signals)))
8179 (setq signals (cdr signals))
8181 (princ "\"") (princ (verilog-sig-name sig)) (princ "\"")
8182 (princ " bits=") (princ (verilog-sig-bits sig))
8183 (princ " cmt=") (princ (verilog-sig-comment sig))
8184 (princ " mem=") (princ (verilog-sig-memory sig))
8185 (princ " enum=") (princ (verilog-sig-enum sig))
8186 (princ " sign=") (princ (verilog-sig-signed sig))
8187 (princ " type=") (princ (verilog-sig-type sig))
8188 (princ " dim=") (princ (verilog-sig-multidim sig))
8189 (princ " modp=") (princ (verilog-sig-modport sig))
8192 (defun verilog-modport-princ (modports &optional header prefix)
8193 "For debug, dump internal MODPORTS structures, with HEADER and PREFIX."
8195 (if header (princ header))
8197 (let ((sig (car modports)))
8198 (setq modports (cdr modports))
8200 (princ "\"") (princ (verilog-modport-name sig)) (princ "\"")
8201 (princ " clockings=") (princ (verilog-modport-clockings sig))
8203 (verilog-decls-princ (verilog-modport-decls sig)
8204 (concat prefix " syms:\n")
8205 (concat prefix " "))))))
8208 ;; Port/Wire/Etc Reading
8211 (defun verilog-read-inst-backward-name ()
8212 "Internal. Move point back to beginning of inst-name."
8213 (verilog-backward-open-paren)
8216 (verilog-re-search-backward-quick "\\()\\|\\b[a-zA-Z0-9`_$]\\|\\]\\)" nil nil) ; ] isn't word boundary
8217 (cond ((looking-at ")")
8218 (verilog-backward-open-paren))
8219 (t (setq done t)))))
8220 (while (looking-at "\\]")
8221 (verilog-backward-open-bracket)
8222 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_$]\\|\\]\\)" nil nil))
8223 (skip-chars-backward "a-zA-Z0-9`_$"))
8225 (defun verilog-read-inst-module-matcher ()
8226 "Set match data 0 with module_name when point is inside instantiation."
8227 (verilog-read-inst-backward-name)
8228 ;; Skip over instantiation name
8229 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_$]\\|)\\)" nil nil) ; ) isn't word boundary
8230 ;; Check for parameterized instantiations
8231 (when (looking-at ")")
8232 (verilog-backward-open-paren)
8233 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_$]" nil nil))
8234 (skip-chars-backward "a-zA-Z0-9'_$")
8235 ;; #1 is legal syntax for gate primitives
8236 (when (save-excursion
8237 (verilog-backward-syntactic-ws-quick)
8238 (eq ?# (char-before)))
8239 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_$]" nil nil)
8240 (skip-chars-backward "a-zA-Z0-9'_$"))
8241 (looking-at "[a-zA-Z0-9`_$]+")
8242 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
8243 (buffer-substring-no-properties (match-beginning 0) (match-end 0))
8244 ;; Caller assumes match-beginning/match-end is still set
8247 (defun verilog-read-inst-module ()
8248 "Return module_name when point is inside instantiation."
8250 (verilog-read-inst-module-matcher)))
8252 (defun verilog-read-inst-name ()
8253 "Return instance_name when point is inside instantiation."
8255 (verilog-read-inst-backward-name)
8256 (looking-at "[a-zA-Z0-9`_$]+")
8257 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
8258 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
8260 (defun verilog-read-module-name ()
8261 "Return module name when after its ( or ;."
8263 (re-search-backward "[(;]")
8264 ;; Due to "module x import y (" we must search for declaration begin
8265 (verilog-re-search-backward-quick verilog-defun-re nil nil)
8266 (goto-char (match-end 0))
8267 (verilog-re-search-forward-quick "\\b[a-zA-Z0-9`_$]+" nil nil)
8268 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
8269 (verilog-symbol-detick
8270 (buffer-substring-no-properties (match-beginning 0) (match-end 0)) t)))
8272 (defun verilog-read-inst-param-value ()
8273 "Return list of parameters and values when point is inside instantiation."
8275 (verilog-read-inst-backward-name)
8276 ;; Skip over instantiation name
8277 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_$]\\|)\\)" nil nil) ; ) isn't word boundary
8278 ;; If there are parameterized instantiations
8279 (when (looking-at ")")
8280 (let ((end-pt (point))
8282 param-name paren-beg-pt param-value)
8283 (verilog-backward-open-paren)
8284 (while (verilog-re-search-forward-quick "\\." end-pt t)
8285 (verilog-re-search-forward-quick "\\([a-zA-Z0-9`_$]\\)" nil nil)
8286 (skip-chars-backward "a-zA-Z0-9'_$")
8287 (looking-at "[a-zA-Z0-9`_$]+")
8288 (setq param-name (buffer-substring-no-properties
8289 (match-beginning 0) (match-end 0)))
8290 (verilog-re-search-forward-quick "(" nil nil)
8291 (setq paren-beg-pt (point))
8292 (verilog-forward-close-paren)
8293 (setq param-value (verilog-string-remove-spaces
8294 (buffer-substring-no-properties
8295 paren-beg-pt (1- (point)))))
8296 (setq params (cons (list param-name param-value) params)))
8299 (defun verilog-read-auto-params (num-param &optional max-param)
8300 "Return parameter list inside auto.
8301 Optional NUM-PARAM and MAX-PARAM check for a specific number of parameters."
8304 ;; /*AUTOPUNT("parameter", "parameter")*/
8306 (while (looking-at "(?\\s *\"\\([^\"]*\\)\"\\s *,?")
8307 (setq olist (cons (match-string 1) olist))
8308 (goto-char (match-end 0))))
8309 (or (eq nil num-param)
8310 (<= num-param (length olist))
8311 (error "%s: Expected %d parameters" (verilog-point-text) num-param))
8312 (if (eq max-param nil) (setq max-param num-param))
8313 (or (eq nil max-param)
8314 (>= max-param (length olist))
8315 (error "%s: Expected <= %d parameters" (verilog-point-text) max-param))
8318 (defun verilog-read-decls ()
8319 "Compute signal declaration information for the current module at point.
8320 Return an array of [outputs inouts inputs wire reg assign const]."
8321 (let ((end-mod-point (or (verilog-get-end-of-defun) (point-max)))
8322 (functask 0) (paren 0) (sig-paren 0) (v2kargs-ok t)
8323 in-modport in-clocking in-ign-to-semi ptype ign-prop
8324 sigs-in sigs-out sigs-inout sigs-var sigs-assign sigs-const
8325 sigs-gparam sigs-intf sigs-modports
8326 vec expect-signal keywd newsig rvalue enum io signed typedefed multidim
8329 ;;(if dbg (setq dbg (concat dbg (format "\n\nverilog-read-decls START PT %s END %s\n" (point) end-mod-point))))
8331 (verilog-beg-of-defun-quick)
8332 (setq sigs-const (verilog-read-auto-constants (point) end-mod-point))
8333 (while (< (point) end-mod-point)
8334 ;;(if dbg (setq dbg (concat dbg (format "Pt %s Vec %s C%c Kwd'%s'\n" (point) vec (following-char) keywd))))
8337 (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
8338 (setq enum (match-string 2)))
8339 (search-forward "\n"))
8340 ((looking-at "/\\*")
8342 (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
8343 (setq enum (match-string 2)))
8344 (or (search-forward "*/")
8345 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
8346 ((looking-at "(\\*")
8347 ;; To advance past either "(*)" or "(* ... *)" don't forward past first *
8349 (or (search-forward "*)")
8350 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
8351 ((eq ?\" (following-char))
8352 (or (re-search-forward "[^\\]\"" nil t) ; don't forward-char first, since we look for a non backslash first
8353 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
8354 ((eq ?\; (following-char))
8355 (cond (in-ign-to-semi ; Such as inside a "import ...;" in a module header
8356 (setq in-ign-to-semi nil))
8357 ((and in-modport (not (eq in-modport t))) ; end of a modport declaration
8358 (verilog-modport-decls-set
8360 (verilog-decls-new sigs-out sigs-inout sigs-in
8361 nil nil nil nil nil nil))
8362 ;; Pop from varstack to restore state to pre-clocking
8363 (setq tmp (car varstack)
8364 varstack (cdr varstack)
8365 sigs-out (aref tmp 0)
8366 sigs-inout (aref tmp 1)
8367 sigs-in (aref tmp 2))
8368 (setq vec nil io nil expect-signal nil newsig nil paren 0 rvalue nil
8369 v2kargs-ok nil in-modport nil ign-prop nil))
8371 (setq vec nil io nil expect-signal nil newsig nil paren 0 rvalue nil
8372 v2kargs-ok nil in-modport nil ign-prop nil)))
8374 ((eq ?= (following-char))
8375 (setq rvalue t newsig nil)
8377 ((and (eq ?, (following-char))
8378 (eq paren sig-paren))
8381 ;; ,'s can occur inside {} & funcs
8382 ((looking-at "[{(]")
8383 (setq paren (1+ paren))
8385 ((looking-at "[})]")
8386 (setq paren (1- paren))
8388 (when (< paren sig-paren)
8389 (setq expect-signal nil rvalue nil))) ; ) that ends variables inside v2k arg list
8390 ((looking-at "\\s-*\\(\\[[^]]+\\]\\)")
8391 (goto-char (match-end 0))
8392 (cond (newsig ; Memory, not just width. Patch last signal added's memory (nth 3)
8393 (setcar (cdr (cdr (cdr newsig)))
8394 (if (verilog-sig-memory newsig)
8395 (concat (verilog-sig-memory newsig) (match-string 1))
8396 (match-string-no-properties 1))))
8397 (vec ; Multidimensional
8398 (setq multidim (cons vec multidim))
8399 (setq vec (verilog-string-replace-matches
8400 "\\s-+" "" nil nil (match-string-no-properties 1))))
8402 (setq vec (verilog-string-replace-matches
8403 "\\s-+" "" nil nil (match-string-no-properties 1))))))
8404 ;; Normal or escaped identifier -- note we remember the \ if escaped
8405 ((looking-at "\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
8406 (goto-char (match-end 0))
8407 (setq keywd (match-string-no-properties 1))
8408 (when (string-match "^\\\\" (match-string 1))
8409 (setq keywd (concat keywd " "))) ; Escaped ID needs space at end
8410 ;; Add any :: package names to same identifier
8411 (while (looking-at "\\s-*::\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
8412 (goto-char (match-end 0))
8413 (setq keywd (concat keywd "::" (match-string 1)))
8414 (when (string-match "^\\\\" (match-string 1))
8415 (setq keywd (concat keywd " ")))) ; Escaped ID needs space at end
8416 (cond ((equal keywd "input")
8417 (setq vec nil enum nil rvalue nil newsig nil signed nil
8418 typedefed nil multidim nil ptype nil modport nil
8419 expect-signal 'sigs-in io t sig-paren paren))
8420 ((equal keywd "output")
8421 (setq vec nil enum nil rvalue nil newsig nil signed nil
8422 typedefed nil multidim nil ptype nil modport nil
8423 expect-signal 'sigs-out io t sig-paren paren))
8424 ((equal keywd "inout")
8425 (setq vec nil enum nil rvalue nil newsig nil signed nil
8426 typedefed nil multidim nil ptype nil modport nil
8427 expect-signal 'sigs-inout io t sig-paren paren))
8428 ((equal keywd "parameter")
8429 (setq vec nil enum nil rvalue nil signed nil
8430 typedefed nil multidim nil ptype nil modport nil
8431 expect-signal 'sigs-gparam io t sig-paren paren))
8432 ((member keywd '("wire" "reg" ; Fast
8434 "tri" "tri0" "tri1" "triand" "trior" "trireg"
8435 "uwire" "wand" "wor"
8436 ;; integer_atom_type
8437 "byte" "shortint" "int" "longint" "integer" "time"
8439 ;; integer_vector_type - "reg" above
8442 "shortreal" "real" "realtime"
8444 "string" "event" "chandle"))
8447 (if typedefed (concat typedefed " " keywd) keywd)))
8448 (t (setq vec nil enum nil rvalue nil signed nil
8449 typedefed nil multidim nil sig-paren paren
8450 expect-signal 'sigs-var modport nil))))
8451 ((equal keywd "assign")
8452 (setq vec nil enum nil rvalue nil signed nil
8453 typedefed nil multidim nil ptype nil modport nil
8454 expect-signal 'sigs-assign sig-paren paren))
8455 ((member keywd '("localparam" "genvar"))
8456 (setq vec nil enum nil rvalue nil signed nil
8457 typedefed nil multidim nil ptype nil modport nil
8458 expect-signal 'sigs-const sig-paren paren))
8459 ((member keywd '("signed" "unsigned"))
8460 (setq signed keywd))
8461 ((member keywd '("assert" "assume" "cover" "expect" "restrict"))
8463 ((member keywd '("class" "covergroup" "function"
8464 "property" "randsequence" "sequence" "task"))
8466 (setq functask (1+ functask))))
8467 ((member keywd '("endclass" "endgroup" "endfunction"
8468 "endproperty" "endsequence" "endtask"))
8469 (setq functask (1- functask)))
8470 ((equal keywd "modport")
8471 (setq in-modport t))
8472 ((equal keywd "clocking")
8473 (setq in-clocking t))
8474 ((equal keywd "import")
8475 (if v2kargs-ok ; import in module header, not a modport import
8476 (setq in-ign-to-semi t rvalue t)))
8477 ((equal keywd "type")
8479 ((equal keywd "var"))
8480 ;; Ifdef? Ignore name of define
8481 ((member keywd '("`ifdef" "`ifndef" "`elsif"))
8485 (verilog-typedef-name-p keywd))
8488 (if typedefed (concat typedefed " " keywd) keywd)))
8489 (t (setq vec nil enum nil rvalue nil signed nil
8490 typedefed keywd ; Have a type
8491 multidim nil sig-paren paren
8492 expect-signal 'sigs-var modport nil))))
8493 ;; Interface with optional modport in v2k arglist?
8494 ;; Skip over parsing modport, and take the interface name as the type
8498 (looking-at "\\s-*\\(\\.\\(\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*\\)\\|\\)\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*"))
8499 (when (match-end 2) (goto-char (match-end 2)))
8500 (setq vec nil enum nil rvalue nil signed nil
8501 typedefed keywd multidim nil ptype nil modport (match-string 2)
8502 newsig nil sig-paren paren
8503 expect-signal 'sigs-intf io t ))
8504 ;; Ignore dotted LHS assignments: "assign foo.bar = z;"
8505 ((looking-at "\\s-*\\.")
8506 (goto-char (match-end 0))
8508 (setq expect-signal nil)))
8509 ;; "modport <keywd>"
8510 ((and (eq in-modport t)
8511 (not (member keywd verilog-keywords)))
8512 (setq in-modport (verilog-modport-new keywd nil nil))
8513 (setq sigs-modports (cons in-modport sigs-modports))
8514 ;; Push old sig values to stack and point to new signal list
8515 (setq varstack (cons (vector sigs-out sigs-inout sigs-in)
8517 (setq sigs-in nil sigs-inout nil sigs-out nil))
8518 ;; "modport x (clocking <keywd>)"
8519 ((and in-modport in-clocking)
8520 (verilog-modport-clockings-add in-modport keywd)
8521 (setq in-clocking nil))
8524 (equal keywd "endclocking"))
8525 (unless (eq in-clocking t)
8526 (verilog-modport-decls-set
8528 (verilog-decls-new sigs-out sigs-inout sigs-in
8529 nil nil nil nil nil nil))
8530 ;; Pop from varstack to restore state to pre-clocking
8531 (setq tmp (car varstack)
8532 varstack (cdr varstack)
8533 sigs-out (aref tmp 0)
8534 sigs-inout (aref tmp 1)
8535 sigs-in (aref tmp 2)))
8536 (setq in-clocking nil))
8537 ;; "clocking <keywd>"
8538 ((and (eq in-clocking t)
8539 (not (member keywd verilog-keywords)))
8540 (setq in-clocking (verilog-modport-new keywd nil nil))
8541 (setq sigs-modports (cons in-clocking sigs-modports))
8542 ;; Push old sig values to stack and point to new signal list
8543 (setq varstack (cons (vector sigs-out sigs-inout sigs-in)
8545 (setq sigs-in nil sigs-inout nil sigs-out nil))
8546 ;; New signal, maybe?
8550 (not (member keywd verilog-keywords)))
8551 ;; Add new signal to expect-signal's variable
8552 ;;(if dbg (setq dbg (concat dbg (format "Pt %s New sig %s'\n" (point) keywd))))
8553 (setq newsig (verilog-sig-new keywd vec nil nil enum signed typedefed multidim modport))
8554 (set expect-signal (cons newsig
8555 (symbol-value expect-signal))))))
8558 (skip-syntax-forward " "))
8560 (setq tmp (verilog-decls-new (nreverse sigs-out)
8561 (nreverse sigs-inout)
8564 (nreverse sigs-modports)
8565 (nreverse sigs-assign)
8566 (nreverse sigs-const)
8567 (nreverse sigs-gparam)
8568 (nreverse sigs-intf)))
8569 ;;(if dbg (verilog-decls-princ tmp))
8572 (defvar verilog-read-sub-decls-in-interfaced nil
8573 "For `verilog-read-sub-decls', process next signal as under interfaced block.")
8575 (defvar verilog-read-sub-decls-gate-ios nil
8576 "For `verilog-read-sub-decls', gate IO pins remaining, nil if non-primitive.")
8579 ;; Prevent compile warnings; these are let's, not globals
8580 ;; Do not remove the eval-when-compile
8581 ;; - we want an error when we are debugging this code if they are refed.
8589 (defvar sigs-out-unk)
8591 ;; These are known to be from other packages and may not be defined
8592 (defvar diff-command)
8593 ;; There are known to be from newer versions of Emacs
8594 (defvar create-lockfiles)
8595 (defvar which-func-modes))
8597 (defun verilog-read-sub-decls-sig (submoddecls comment port sig vec multidim mem)
8598 "For `verilog-read-sub-decls-line', add a signal."
8599 ;; sig eq t to indicate .name syntax
8600 ;;(message "vrsds: %s(%S)" port sig)
8601 (let ((dotname (eq sig t))
8604 (setq port (verilog-symbol-detick-denumber port))
8605 (setq sig (if dotname port (verilog-symbol-detick-denumber sig)))
8606 (if vec (setq vec (verilog-symbol-detick-denumber vec)))
8607 (if multidim (setq multidim (mapcar `verilog-symbol-detick-denumber multidim)))
8608 (if mem (setq mem (verilog-symbol-detick-denumber mem)))
8609 (unless (or (not sig)
8610 (equal sig "")) ; Ignore .foo(1'b1) assignments
8611 (cond ((or (setq portdata (assoc port (verilog-decls-get-inouts submoddecls)))
8612 (equal "inout" verilog-read-sub-decls-gate-ios))
8614 (cons (verilog-sig-new
8616 (if dotname (verilog-sig-bits portdata) vec)
8617 (concat "To/From " comment)
8620 (verilog-sig-signed portdata)
8621 (unless (member (verilog-sig-type portdata) '("wire" "reg"))
8622 (verilog-sig-type portdata))
8625 ((or (setq portdata (assoc port (verilog-decls-get-outputs submoddecls)))
8626 (equal "output" verilog-read-sub-decls-gate-ios))
8628 (cons (verilog-sig-new
8630 (if dotname (verilog-sig-bits portdata) vec)
8631 (concat "From " comment)
8634 (verilog-sig-signed portdata)
8635 ;; Though ok in SV, in V2K code, propagating the
8636 ;; "reg" in "output reg" upwards isn't legal.
8637 ;; Also for backwards compatibility we don't propagate
8638 ;; "input wire" upwards.
8639 ;; See also `verilog-signals-edit-wire-reg'.
8640 (unless (member (verilog-sig-type portdata) '("wire" "reg"))
8641 (verilog-sig-type portdata))
8644 ((or (setq portdata (assoc port (verilog-decls-get-inputs submoddecls)))
8645 (equal "input" verilog-read-sub-decls-gate-ios))
8647 (cons (verilog-sig-new
8649 (if dotname (verilog-sig-bits portdata) vec)
8650 (concat "To " comment)
8653 (verilog-sig-signed portdata)
8654 (unless (member (verilog-sig-type portdata) '("wire" "reg"))
8655 (verilog-sig-type portdata))
8658 ((setq portdata (assoc port (verilog-decls-get-interfaces submoddecls)))
8660 (cons (verilog-sig-new
8662 (if dotname (verilog-sig-bits portdata) vec)
8663 (concat "To/From " comment)
8666 (verilog-sig-signed portdata)
8667 (verilog-sig-type portdata)
8670 ((setq portdata (and verilog-read-sub-decls-in-interfaced
8671 (assoc port (verilog-decls-get-vars submoddecls))))
8673 (cons (verilog-sig-new
8675 (if dotname (verilog-sig-bits portdata) vec)
8676 (concat "To/From " comment)
8679 (verilog-sig-signed portdata)
8680 (verilog-sig-type portdata)
8683 ;; (t -- warning pin isn't defined.) ; Leave for lint tool
8686 (defun verilog-read-sub-decls-expr (submoddecls comment port expr)
8687 "For `verilog-read-sub-decls-line', parse a subexpression and add signals."
8688 ;;(message "vrsde: `%s'" expr)
8689 ;; Replace special /*[....]*/ comments inserted by verilog-auto-inst-port
8690 (setq expr (verilog-string-replace-matches "/\\*\\(\\.?\\[[^*]+\\]\\)\\*/" "\\1" nil nil expr))
8691 ;; Remove front operators
8692 (setq expr (verilog-string-replace-matches "^\\s-*[---+~!|&]+\\s-*" "" nil nil expr))
8695 ;; {..., a, b} requires us to recurse on a,b
8696 ;; To support {#{},{#{a,b}} we'll just split everything on [{},]
8697 ((string-match "^\\s-*{\\(.*\\)}\\s-*$" expr)
8698 (unless verilog-auto-ignore-concat
8699 (let ((mlst (split-string (match-string 1 expr) "[{},]"))
8701 (while (setq mstr (pop mlst))
8702 (verilog-read-sub-decls-expr submoddecls comment port mstr)))))
8704 (let (sig vec multidim mem)
8705 ;; Remove leading reduction operators, etc
8706 (setq expr (verilog-string-replace-matches "^\\s-*[---+~!|&]+\\s-*" "" nil nil expr))
8707 ;;(message "vrsde-ptop: `%s'" expr)
8708 (cond ; Find \signal. Final space is part of escaped signal name
8709 ((string-match "^\\s-*\\(\\\\[^ \t\n\f]+\\s-\\)" expr)
8710 ;;(message "vrsde-s: `%s'" (match-string 1 expr))
8711 (setq sig (match-string 1 expr)
8712 expr (substring expr (match-end 0))))
8714 ((string-match "^\\s-*\\([a-zA-Z_][a-zA-Z_0-9]*\\)" expr)
8715 ;;(message "vrsde-s: `%s'" (match-string 1 expr))
8716 (setq sig (verilog-string-remove-spaces (match-string 1 expr))
8717 expr (substring expr (match-end 0)))))
8718 ;; Find [vector] or [multi][multi][multi][vector]
8719 (while (string-match "^\\s-*\\(\\[[^]]+\\]\\)" expr)
8720 ;;(message "vrsde-v: `%s'" (match-string 1 expr))
8721 (when vec (setq multidim (cons vec multidim)))
8722 (setq vec (match-string 1 expr)
8723 expr (substring expr (match-end 0))))
8724 ;; Find .[unpacked_memory] or .[unpacked][unpacked]...
8725 (while (string-match "^\\s-*\\.\\(\\[[^]]+\\]\\)" expr)
8726 ;;(message "vrsde-m: `%s'" (match-string 1 expr))
8727 (setq mem (match-string 1 expr)
8728 expr (substring expr (match-end 0))))
8729 ;; If found signal, and nothing unrecognized, add the signal
8730 ;;(message "vrsde-rem: `%s'" expr)
8731 (when (and sig (string-match "^\\s-*$" expr))
8732 (verilog-read-sub-decls-sig submoddecls comment port sig vec multidim mem))))))
8734 (defun verilog-read-sub-decls-line (submoddecls comment)
8735 "For `verilog-read-sub-decls', read lines of port defs until none match.
8736 Inserts the list of signals found, using submodi to look up each port."
8742 (cond ((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*(\\s-*")
8743 (setq port (match-string-no-properties 1))
8744 (goto-char (match-end 0)))
8746 ((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*(\\s-*")
8747 (setq port (concat (match-string-no-properties 1) " ")) ; escaped id's need trailing space
8748 (goto-char (match-end 0)))
8750 ((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*[,)/]")
8751 (verilog-read-sub-decls-sig
8752 submoddecls comment (match-string-no-properties 1) t ; sig==t for .name
8753 nil nil nil) ; vec multidim mem
8756 ((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*[,)/]")
8757 (verilog-read-sub-decls-sig
8758 submoddecls comment (concat (match-string-no-properties 1) " ") t ; sig==t for .name
8759 nil nil nil) ; vec multidim mem
8762 ((looking-at "\\s-*\\.[^(]*(")
8763 (setq port nil) ; skip this line
8764 (goto-char (match-end 0)))
8766 (setq port nil done t))) ; Unknown, ignore rest of line
8767 ;; Get signal name. Point is at the first-non-space after (
8768 ;; We intentionally ignore (non-escaped) signals with .s in them
8769 ;; this prevents AUTOWIRE etc from noticing hierarchical sigs.
8771 (cond ((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*)")
8772 (verilog-read-sub-decls-sig
8773 submoddecls comment port
8774 (verilog-string-remove-spaces (match-string-no-properties 1)) ; sig
8775 nil nil nil)) ; vec multidim mem
8777 ((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*)")
8778 (verilog-read-sub-decls-sig
8779 submoddecls comment port
8780 (verilog-string-remove-spaces (match-string-no-properties 1)) ; sig
8781 (match-string-no-properties 2) nil nil)) ; vec multidim mem
8782 ;; Fastpath was above looking-at's.
8783 ;; For something more complicated invoke a parser
8784 ((looking-at "[^)]+")
8785 (verilog-read-sub-decls-expr
8786 submoddecls comment port
8787 (buffer-substring-no-properties
8788 (point) (1- (progn (search-backward "(") ; start at (
8789 (verilog-forward-sexp-ign-cmt 1)
8790 (point)))))))) ; expr
8792 (forward-line 1)))))
8794 (defun verilog-read-sub-decls-gate (submoddecls comment submod end-inst-point)
8795 "For `verilog-read-sub-decls', read lines of UDP gate decl until none match.
8796 Inserts the list of signals found."
8798 (let ((iolist (cdr (assoc submod verilog-gate-ios))))
8799 (while (< (point) end-inst-point)
8800 ;; Get primitive's signal name, as will never have port, and no trailing )
8801 (cond ((looking-at "//")
8802 (search-forward "\n"))
8803 ((looking-at "/\\*")
8804 (or (search-forward "*/")
8805 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
8806 ((looking-at "(\\*")
8807 ;; To advance past either "(*)" or "(* ... *)" don't forward past first *
8809 (or (search-forward "*)")
8810 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
8811 ;; On pins, parse and advance to next pin
8812 ;; Looking at pin, but *not* an // Output comment, or ) to end the inst
8813 ((looking-at "\\s-*[a-zA-Z0-9`_$({}\\\\][^,]*")
8814 (goto-char (match-end 0))
8815 (setq verilog-read-sub-decls-gate-ios (or (car iolist) "input")
8816 iolist (cdr iolist))
8817 (verilog-read-sub-decls-expr
8818 submoddecls comment "primitive_port"
8822 (skip-syntax-forward " ")))))))
8824 (defun verilog-read-sub-decls ()
8825 "Internally parse signals going to modules under this module.
8826 Return an array of [ outputs inouts inputs ] signals for modules that are
8827 instantiated in this module. For example if declare A A (.B(SIG)) and SIG
8828 is an output, then SIG will be included in the list.
8830 This only works on instantiations created with /*AUTOINST*/ converted by
8831 \\[verilog-auto-inst]. Otherwise, it would have to read in the whole
8832 component library to determine connectivity of the design.
8834 One work around for this problem is to manually create // Inputs and //
8835 Outputs comments above subcell signals, for example:
8843 (let ((end-mod-point (verilog-get-end-of-defun))
8844 st-point end-inst-point
8845 ;; below 3 modified by verilog-read-sub-decls-line
8846 sigs-out sigs-inout sigs-in sigs-intf sigs-intfd)
8847 (verilog-beg-of-defun-quick)
8848 (while (verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-mod-point t)
8850 (goto-char (match-beginning 0))
8851 (unless (verilog-inside-comment-or-string-p)
8852 ;; Attempt to snarf a comment
8853 (let* ((submod (verilog-read-inst-module))
8854 (inst (verilog-read-inst-name))
8855 (subprim (member submod verilog-gate-keywords))
8856 (comment (concat inst " of " submod ".v"))
8857 submodi submoddecls)
8860 (setq submodi `primitive
8861 submoddecls (verilog-decls-new nil nil nil nil nil nil nil nil nil)
8862 comment (concat inst " of " submod))
8863 (verilog-backward-open-paren)
8864 (setq end-inst-point (save-excursion (verilog-forward-sexp-ign-cmt 1)
8868 (verilog-read-sub-decls-gate submoddecls comment submod end-inst-point))
8871 (when (setq submodi (verilog-modi-lookup submod t))
8872 (setq submoddecls (verilog-modi-get-decls submodi)
8873 verilog-read-sub-decls-gate-ios nil)
8874 (verilog-backward-open-paren)
8875 (setq end-inst-point (save-excursion (verilog-forward-sexp-ign-cmt 1)
8878 ;; This could have used a list created by verilog-auto-inst
8879 ;; However I want it to be runnable even on user's manually added signals
8880 (let ((verilog-read-sub-decls-in-interfaced t))
8881 (while (re-search-forward "\\s *(?\\s *// Interfaced" end-inst-point t)
8882 (verilog-read-sub-decls-line submoddecls comment))) ; Modifies sigs-ifd
8883 (goto-char st-point)
8884 (while (re-search-forward "\\s *(?\\s *// Interfaces" end-inst-point t)
8885 (verilog-read-sub-decls-line submoddecls comment)) ; Modifies sigs-out
8886 (goto-char st-point)
8887 (while (re-search-forward "\\s *(?\\s *// Outputs" end-inst-point t)
8888 (verilog-read-sub-decls-line submoddecls comment)) ; Modifies sigs-out
8889 (goto-char st-point)
8890 (while (re-search-forward "\\s *(?\\s *// Inouts" end-inst-point t)
8891 (verilog-read-sub-decls-line submoddecls comment)) ; Modifies sigs-inout
8892 (goto-char st-point)
8893 (while (re-search-forward "\\s *(?\\s *// Inputs" end-inst-point t)
8894 (verilog-read-sub-decls-line submoddecls comment)) ; Modifies sigs-in
8896 ;; Combine duplicate bits
8897 ;;(setq rr (vector sigs-out sigs-inout sigs-in))
8898 (verilog-subdecls-new
8899 (verilog-signals-combine-bus (nreverse sigs-out))
8900 (verilog-signals-combine-bus (nreverse sigs-inout))
8901 (verilog-signals-combine-bus (nreverse sigs-in))
8902 (verilog-signals-combine-bus (nreverse sigs-intf))
8903 (verilog-signals-combine-bus (nreverse sigs-intfd))))))
8905 (defun verilog-read-inst-pins ()
8906 "Return an array of [ pins ] for the current instantiation at point.
8907 For example if declare A A (.B(SIG)) then B will be included in the list."
8909 (let ((end-mod-point (point)) ; presume at /*AUTOINST*/ point
8911 (verilog-backward-open-paren)
8912 (while (re-search-forward "\\.\\([^(,) \t\n\f]*\\)\\s-*" end-mod-point t)
8913 (setq pin (match-string 1))
8914 (unless (verilog-inside-comment-or-string-p)
8915 (setq pins (cons (list pin) pins))
8916 (when (looking-at "(")
8917 (verilog-forward-sexp-ign-cmt 1))))
8920 (defun verilog-read-arg-pins ()
8921 "Return an array of [ pins ] for the current argument declaration at point."
8923 (let ((end-mod-point (point)) ; presume at /*AUTOARG*/ point
8925 (verilog-backward-open-paren)
8926 (while (re-search-forward "\\([a-zA-Z0-9$_.%`]+\\)" end-mod-point t)
8927 (setq pin (match-string 1))
8928 (unless (verilog-inside-comment-or-string-p)
8929 (setq pins (cons (list pin) pins))))
8932 (defun verilog-read-auto-constants (beg end-mod-point)
8933 "Return a list of AUTO_CONSTANTs used in the region from BEG to END-MOD-POINT."
8936 (let (sig-list tpl-end-pt)
8938 (while (re-search-forward "\\<AUTO_CONSTANT" end-mod-point t)
8939 (if (not (looking-at "\\s *("))
8940 (error "%s: Missing () after AUTO_CONSTANT" (verilog-point-text)))
8941 (search-forward "(" end-mod-point)
8942 (setq tpl-end-pt (save-excursion
8944 (verilog-forward-sexp-cmt 1) ; Moves to paren that closes argdecl's
8947 (while (re-search-forward "\\s-*\\([\"a-zA-Z0-9$_.%`]+\\)\\s-*,*" tpl-end-pt t)
8948 (setq sig-list (cons (list (match-string 1) nil nil) sig-list))))
8951 (defvar verilog-cache-has-lisp nil "True if any AUTO_LISP in buffer.")
8952 (make-variable-buffer-local 'verilog-cache-has-lisp)
8954 (defun verilog-read-auto-lisp-present ()
8955 "Set `verilog-cache-has-lisp' if any AUTO_LISP in this buffer."
8957 (goto-char (point-min))
8958 (setq verilog-cache-has-lisp (re-search-forward "\\<AUTO_LISP(" nil t))))
8960 (defun verilog-read-auto-lisp (start end)
8961 "Look for and evaluate an AUTO_LISP between START and END.
8962 Must call `verilog-read-auto-lisp-present' before this function."
8963 ;; This function is expensive for large buffers, so we cache if any AUTO_LISP exists
8964 (when verilog-cache-has-lisp
8967 (while (re-search-forward "\\<AUTO_LISP(" end t)
8969 (let* ((beg-pt (prog1 (point)
8970 (verilog-forward-sexp-cmt 1))) ; Closing paren
8972 (verilog-in-hooks t))
8973 (eval-region beg-pt end-pt nil))))))
8975 (defun verilog-read-always-signals-recurse
8976 (exit-keywd rvalue temp-next)
8977 "Recursive routine for parentheses/bracket matching.
8978 EXIT-KEYWD is expression to stop at, nil if top level.
8979 RVALUE is true if at right hand side of equal.
8980 IGNORE-NEXT is true to ignore next token, fake from inside case statement."
8981 (let* ((semi-rvalue (equal "endcase" exit-keywd)) ; true if after a ; we are looking for rvalue
8982 keywd last-keywd sig-tolk sig-last-tolk gotend got-sig got-list end-else-check
8984 ;;(if dbg (setq dbg (concat dbg (format "Recursion %S %S %S\n" exit-keywd rvalue temp-next))))
8985 (while (not (or (eobp) gotend))
8988 (search-forward "\n"))
8989 ((looking-at "/\\*")
8990 (or (search-forward "*/")
8991 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
8992 ((looking-at "(\\*")
8993 ;; To advance past either "(*)" or "(* ... *)" don't forward past first *
8995 (or (search-forward "*)")
8996 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
8997 (t (setq keywd (buffer-substring-no-properties
8999 (save-excursion (when (eq 0 (skip-chars-forward "a-zA-Z0-9$_.%`"))
9002 sig-last-tolk sig-tolk
9004 ;;(if dbg (setq dbg (concat dbg (format "\tPt=%S %S\trv=%S in=%S ee=%S gs=%S\n" (point) keywd rvalue ignore-next end-else-check got-sig))))
9007 (or (re-search-forward "[^\\]\"" nil t)
9008 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
9009 ;; else at top level loop, keep parsing
9010 ((and end-else-check (equal keywd "else"))
9011 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else %s\n" keywd))))
9012 ;; no forward movement, want to see else in lower loop
9013 (setq end-else-check nil))
9014 ;; End at top level loop
9015 ((and end-else-check (looking-at "[^ \t\n\f]"))
9016 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else-other %s\n" keywd))))
9019 ((and exit-keywd (equal keywd exit-keywd))
9021 (forward-char (length keywd)))
9022 ;; Standard tokens...
9024 (setq ignore-next nil rvalue semi-rvalue)
9025 ;; Final statement at top level loop?
9026 (when (not exit-keywd)
9027 ;;(if dbg (setq dbg (concat dbg (format "\ttop-end-check %s\n" keywd))))
9028 (setq end-else-check t))
9031 (if (looking-at "'[sS]?[hdxboHDXBO]?[ \t]*[0-9a-fA-F_xzXZ?]+")
9032 (goto-char (match-end 0))
9034 ((equal keywd ":") ; Case statement, begin/end label, x?y:z
9035 (cond ((equal "endcase" exit-keywd) ; case x: y=z; statement next
9036 (setq ignore-next nil rvalue nil))
9037 ((equal "?" exit-keywd) ; x?y:z rvalue
9039 ((equal "]" exit-keywd) ; [x:y] rvalue
9041 (got-sig ; label: statement
9042 (setq ignore-next nil rvalue semi-rvalue got-sig nil))
9043 ((not rvalue) ; begin label
9044 (setq ignore-next t rvalue nil)))
9048 ;;(if dbg (setq dbg (concat dbg (format "\t\tequal got-sig=%S got-list=%s\n" got-sig got-list))))
9049 (set got-list (cons got-sig (symbol-value got-list)))
9052 (if (eq (char-before) ?< )
9053 (setq sigs-out-d (append sigs-out-d sigs-out-unk)
9055 (setq sigs-out-i (append sigs-out-i sigs-out-unk)
9057 (setq ignore-next nil rvalue t)
9061 (verilog-read-always-signals-recurse ":" rvalue nil))
9064 (verilog-read-always-signals-recurse "]" t nil))
9067 (cond (sig-last-tolk ; Function call; zap last signal
9068 (setq got-sig nil)))
9069 (cond ((equal last-keywd "for")
9070 ;; temp-next: Variables on LHS are lvalues, but generally we want
9071 ;; to ignore them, assuming they are loop increments
9072 (verilog-read-always-signals-recurse ";" nil t)
9073 (verilog-read-always-signals-recurse ";" t nil)
9074 (verilog-read-always-signals-recurse ")" nil nil))
9075 (t (verilog-read-always-signals-recurse ")" t nil))))
9076 ((equal keywd "begin")
9077 (skip-syntax-forward "w_")
9078 (verilog-read-always-signals-recurse "end" nil nil)
9079 ;;(if dbg (setq dbg (concat dbg (format "\tgot-end %s\n" exit-keywd))))
9080 (setq ignore-next nil rvalue semi-rvalue)
9081 (if (not exit-keywd) (setq end-else-check t)))
9082 ((member keywd '("case" "casex" "casez"))
9083 (skip-syntax-forward "w_")
9084 (verilog-read-always-signals-recurse "endcase" t nil)
9085 (setq ignore-next nil rvalue semi-rvalue)
9086 (if (not exit-keywd) (setq gotend t))) ; top level begin/end
9087 ((string-match "^[$`a-zA-Z_]" keywd) ; not exactly word constituent
9088 (cond ((member keywd '("`ifdef" "`ifndef" "`elsif"))
9089 (setq ignore-next t))
9091 (member keywd verilog-keywords)
9092 (string-match "^\\$" keywd)) ; PLI task
9093 (setq ignore-next nil))
9095 (setq keywd (verilog-symbol-detick-denumber keywd))
9097 (set got-list (cons got-sig (symbol-value got-list)))
9098 ;;(if dbg (setq dbg (concat dbg (format "\t\tgot-sig=%S got-list=%S\n" got-sig got-list))))
9100 (setq got-list (cond (temp-next 'sigs-temp)
9103 got-sig (if (or (not keywd)
9104 (assoc keywd (symbol-value got-list)))
9105 nil (list keywd nil nil))
9108 (skip-chars-forward "a-zA-Z0-9$_.%`"))
9111 ;; End of non-comment token
9112 (setq last-keywd keywd)))
9113 (skip-syntax-forward " "))
9114 ;; Append the final pending signal
9116 ;;(if dbg (setq dbg (concat dbg (format "\t\tfinal got-sig=%S got-list=%s\n" got-sig got-list))))
9117 (set got-list (cons got-sig (symbol-value got-list)))
9119 ;;(if dbg (setq dbg (concat dbg (format "ENDRecursion %s\n" exit-keywd))))
9122 (defun verilog-read-always-signals ()
9123 "Parse always block at point and return list of (outputs inout inputs)."
9126 sigs-out-d sigs-out-i sigs-out-unk sigs-temp sigs-in)
9127 (verilog-read-always-signals-recurse nil nil nil)
9128 (setq sigs-out-i (append sigs-out-i sigs-out-unk)
9130 ;;(if dbg (with-current-buffer (get-buffer-create "*vl-dbg*")) (delete-region (point-min) (point-max)) (insert dbg) (setq dbg ""))
9131 ;; Return what was found
9132 (verilog-alw-new sigs-out-d sigs-out-i sigs-temp sigs-in))))
9134 (defun verilog-read-instants ()
9135 "Parse module at point and return list of ( ( file instance ) ... )."
9136 (verilog-beg-of-defun-quick)
9137 (let* ((end-mod-point (verilog-get-end-of-defun))
9139 (instants-list nil))
9141 (while (< (point) end-mod-point)
9142 ;; Stay at level 0, no comments
9144 (setq state (parse-partial-sexp (point) end-mod-point 0 t nil))
9145 (or (> (car state) 0) ; in parens
9146 (nth 5 state) ; comment
9150 (if (looking-at "^\\s-*\\([a-zA-Z0-9`_$]+\\)\\s-+\\([a-zA-Z0-9`_$]+\\)\\s-*(")
9151 ;;(if (looking-at "^\\(.+\\)$")
9152 (let ((module (match-string 1))
9153 (instant (match-string 2)))
9154 (if (not (member module verilog-keywords))
9155 (setq instants-list (cons (list module instant) instants-list)))))
9160 (defun verilog-read-auto-template-middle ()
9161 "With point in middle of an AUTO_TEMPLATE, parse it.
9162 Returns REGEXP and list of ( (signal_name connection_name)... )."
9165 (let ((tpl-regexp "\\([0-9]+\\)")
9166 (lineno -1) ; -1 to offset for the AUTO_TEMPLATE's newline
9168 tpl-sig-list tpl-wild-list tpl-end-pt rep)
9170 ;; We reserve @"..." for future lisp expressions that evaluate
9171 ;; once-per-AUTOINST
9172 (when (looking-at "\\s-*\"\\([^\"]*\\)\"")
9173 (setq tpl-regexp (match-string 1))
9174 (goto-char (match-end 0)))
9175 (search-forward "(")
9176 ;; Parse lines in the template
9177 (when (or verilog-auto-inst-template-numbers
9178 verilog-auto-template-warn-unused)
9180 (let ((pre-pt (point)))
9181 (goto-char (point-min))
9182 (while (search-forward "AUTO_TEMPLATE" pre-pt t)
9183 (setq templateno (1+ templateno)))
9184 (while (< (point) pre-pt)
9186 (setq lineno (1+ lineno))))))
9187 (setq tpl-end-pt (save-excursion
9189 (verilog-forward-sexp-cmt 1) ; Moves to paren that closes argdecl's
9193 (while (< (point) tpl-end-pt)
9194 (cond ((looking-at "\\s-*\\.\\([a-zA-Z0-9`_$]+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
9197 (match-string-no-properties 1)
9198 (match-string-no-properties 2)
9201 (goto-char (match-end 0)))
9204 ;; Regexp bug in XEmacs disallows ][ inside [], and wants + last
9205 "\\s-*\\.\\(\\([a-zA-Z0-9`_$+@^.*?|---]+\\|[][]\\|\\\\[()|]\\)+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
9206 (setq rep (match-string-no-properties 3))
9207 (goto-char (match-end 0))
9211 (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil
9217 ((looking-at "[ \t\f]+")
9218 (goto-char (match-end 0)))
9220 (setq lineno (1+ lineno))
9221 (goto-char (match-end 0)))
9223 (search-forward "\n")
9224 (setq lineno (1+ lineno)))
9225 ((looking-at "/\\*")
9227 (or (search-forward "*/")
9228 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
9230 (error "%s: AUTO_TEMPLATE parsing error: %s"
9231 (verilog-point-text)
9232 (progn (looking-at ".*$") (match-string 0))))))
9235 (list tpl-sig-list tpl-wild-list)))))
9237 (defun verilog-read-auto-template (module)
9238 "Look for an auto_template for the instantiation of the given MODULE.
9239 If found returns `verilog-read-auto-template-inside' structure."
9243 ;; Note this search is expensive, as we hunt from mod-begin to point
9244 ;; for every instantiation. Likewise in verilog-read-auto-lisp.
9245 ;; So, we look first for an exact string rather than a slow regexp.
9246 ;; Someday we may keep a cache of every template, but this would also
9247 ;; need to record the relative position of each AUTOINST, as multiple
9248 ;; templates exist for each module, and we're inserting lines.
9250 ;; See also regexp in `verilog-auto-template-lint'
9251 (verilog-re-search-backward-substr
9253 (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)
9254 ;; Also try forward of this AUTOINST
9255 ;; This is for historical support; this isn't speced as working
9258 (verilog-re-search-forward-substr
9260 (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)))
9261 (goto-char (match-end 0))
9262 (verilog-read-auto-template-middle))
9263 ;; If no template found
9264 (t (vector "" nil))))))
9265 ;;(progn (find-file "auto-template.v") (verilog-read-auto-template "ptl_entry"))
9267 (defvar verilog-auto-template-hits nil "Successful lookups with `verilog-read-auto-template-hit'.")
9268 (make-variable-buffer-local 'verilog-auto-template-hits)
9270 (defun verilog-read-auto-template-init ()
9271 "Initialize `verilog-read-auto-template'."
9272 (when (eval-when-compile (fboundp 'make-hash-table)) ; else feature not allowed
9273 (when verilog-auto-template-warn-unused
9274 (setq verilog-auto-template-hits
9275 (make-hash-table :test 'equal :rehash-size 4.0)))))
9277 (defun verilog-read-auto-template-hit (tpl-ass)
9278 "Record that TPL-ASS template from `verilog-read-auto-template' was used."
9279 (when (eval-when-compile (fboundp 'make-hash-table)) ; else feature not allowed
9280 (when verilog-auto-template-warn-unused
9281 (unless verilog-auto-template-hits
9282 (verilog-read-auto-template-init))
9283 (puthash (vector (nth 2 tpl-ass) (nth 3 tpl-ass)) t
9284 verilog-auto-template-hits))))
9286 (defun verilog-set-define (defname defvalue &optional buffer enumname)
9287 "Set the definition DEFNAME to the DEFVALUE in the given BUFFER.
9288 Optionally associate it with the specified enumeration ENUMNAME."
9289 (with-current-buffer (or buffer (current-buffer))
9290 ;; Namespace intentionally short for AUTOs and compatibility
9291 (let ((mac (intern (concat "vh-" defname))))
9292 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
9293 ;; Need to define to a constant if no value given
9294 (set (make-local-variable mac)
9295 (if (equal defvalue "") "1" defvalue)))
9297 ;; Namespace intentionally short for AUTOs and compatibility
9298 (let ((enumvar (intern (concat "venum-" enumname))))
9299 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
9300 (unless (boundp enumvar) (set enumvar nil))
9301 (add-to-list (make-local-variable enumvar) defname)))))
9303 (defun verilog-read-defines (&optional filename recurse subcall)
9304 "Read \\=`defines and parameters for the current file, or optional FILENAME.
9305 If the filename is provided, `verilog-library-flags' will be used to
9306 resolve it. If optional RECURSE is non-nil, recurse through \\=`includes.
9308 Parameters must be simple assignments to constants, or have their own
9309 \"parameter\" label rather than a list of parameters. Thus:
9311 parameter X = 5, Y = 10; // Ok
9312 parameter X = {1\\='b1, 2\\='h2}; // Ok
9313 parameter X = {1\\='b1, 2\\='h2}, Y = 10; // Bad, make into 2 parameter lines
9315 Defines must be simple text substitutions, one on a line, starting
9316 at the beginning of the line. Any ifdefs or multiline comments around the
9319 Defines are stored inside Emacs variables using the name vh-{definename}.
9321 This function is useful for setting vh-* variables. The file variables
9322 feature can be used to set defines that `verilog-mode' can see; put at the
9323 *END* of your file something like:
9326 // vh-macro:\"macro_definition\"
9329 If macros are defined earlier in the same file and you want their values,
9330 you can read them automatically (provided `enable-local-eval' is on):
9333 // eval:(verilog-read-defines)
9334 // eval:(verilog-read-defines \"group_standard_includes.v\")
9337 Note these are only read when the file is first visited, you must use
9338 \\[find-alternate-file] RET to have these take effect after editing them!
9340 If you want to disable the \"Process `eval' or hook local variables\"
9341 warning message, you need to add to your init file:
9343 (setq enable-local-eval t)"
9344 (let ((origbuf (current-buffer)))
9346 (unless subcall (verilog-getopt-flags))
9348 (let ((fns (verilog-library-filenames filename (buffer-file-name))))
9350 (set-buffer (find-file-noselect (car fns)))
9351 (error "%s: Can't find verilog-read-defines file: %s"
9352 (verilog-point-text) filename))))
9354 (goto-char (point-min))
9355 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
9356 (let ((inc (verilog-string-replace-matches
9357 "\"" "" nil nil (match-string-no-properties 1))))
9358 (unless (verilog-inside-comment-or-string-p)
9359 (verilog-read-defines inc recurse t)))))
9361 ;; note we don't use verilog-re... it's faster this way, and that
9362 ;; function has problems when comments are at the end of the define
9363 (goto-char (point-min))
9364 (while (re-search-forward "^\\s-*`define\\s-+\\([a-zA-Z0-9_$]+\\)\\s-+\\(.*\\)$" nil t)
9365 (let ((defname (match-string-no-properties 1))
9366 (defvalue (match-string-no-properties 2)))
9367 (unless (verilog-inside-comment-or-string-p (match-beginning 0))
9368 (setq defvalue (verilog-string-replace-matches "\\s-*/[/*].*$" "" nil nil defvalue))
9369 (verilog-set-define defname defvalue origbuf))))
9370 ;; Hack: Read parameters
9371 (goto-char (point-min))
9372 (while (re-search-forward
9373 "^\\s-*\\(parameter\\|localparam\\)\\(\\s-*\\[[^]]*\\]\\)?\\s-*" nil t)
9375 ;; The primary way of getting defines is verilog-read-decls
9376 ;; However, that isn't called yet for included files, so we'll add another scheme
9377 (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
9378 (setq enumname (match-string-no-properties 2)))
9379 (forward-comment 99999)
9380 (while (looking-at (concat "\\s-*,?\\s-*\\(?:/[/*].*?$\\)?\\s-*\\([a-zA-Z0-9_$]+\\)"
9381 "\\s-*=\\s-*\\([^;,]*\\),?\\s-*\\(/[/*].*?$\\)?\\s-*"))
9382 (unless (verilog-inside-comment-or-string-p (match-beginning 0))
9383 (verilog-set-define (match-string-no-properties 1)
9384 (match-string-no-properties 2) origbuf enumname))
9385 (goto-char (match-end 0))
9386 (forward-comment 99999)))))))
9388 (defun verilog-read-includes ()
9389 "Read \\=`includes for the current file.
9390 This will find all of the \\=`includes which are at the beginning of lines,
9391 ignoring any ifdefs or multiline comments around them.
9392 `verilog-read-defines' is then performed on the current and each included
9395 It is often useful put at the *END* of your file something like:
9398 // eval:(verilog-read-defines)
9399 // eval:(verilog-read-includes)
9402 Note includes are only read when the file is first visited, you must use
9403 \\[find-alternate-file] RET to have these take effect after editing them!
9405 It is good to get in the habit of including all needed files in each .v
9406 file that needs it, rather than waiting for compile time. This will aid
9407 this process, Verilint, and readability. To prevent defining the same
9408 variable over and over when many modules are compiled together, put a test
9409 around the inside each include file:
9411 foo.v (an include file):
9412 \\=`ifdef _FOO_V // include if not already included
9415 ... contents of file
9416 \\=`endif // _FOO_V"
9417 ;;slow: (verilog-read-defines nil t)
9419 (verilog-getopt-flags)
9420 (goto-char (point-min))
9421 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
9422 (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string 1))))
9423 (verilog-read-defines inc nil t)))))
9425 (defun verilog-read-signals (&optional start end)
9426 "Return a simple list of all possible signals in the file.
9427 Bounded by optional region from START to END. Overly aggressive but fast.
9428 Some macros and such are also found and included. For dinotrace.el."
9429 (let (sigs-all keywd)
9430 (progn;save-excursion
9431 (goto-char (or start (point-min)))
9432 (setq end (or end (point-max)))
9433 (while (re-search-forward "[\"/a-zA-Z_.%`]" end t)
9437 (search-forward "\n"))
9438 ((looking-at "/\\*")
9439 (search-forward "*/"))
9440 ((looking-at "(\\*")
9441 (or (looking-at "(\\*\\s-*)") ; It's an "always @ (*)"
9442 (search-forward "*)")))
9443 ((eq ?\" (following-char))
9444 (re-search-forward "[^\\]\"")) ; don't forward-char first, since we look for a non backslash first
9445 ((looking-at "\\s-*\\([a-zA-Z0-9$_.%`]+\\)")
9446 (goto-char (match-end 0))
9447 (setq keywd (match-string-no-properties 1))
9448 (or (member keywd verilog-keywords)
9449 (member keywd sigs-all)
9450 (setq sigs-all (cons keywd sigs-all))))
9451 (t (forward-char 1))))
9456 ;; Argument file parsing
9459 (defun verilog-getopt (arglist)
9460 "Parse -f, -v etc arguments in ARGLIST list or string."
9461 (unless (listp arglist) (setq arglist (list arglist)))
9462 (let ((space-args '())
9464 ;; Split on spaces, so users can pass whole command lines
9466 (setq arg (car arglist)
9467 arglist (cdr arglist))
9468 (while (string-match "^\\([^ \t\n\f]+\\)[ \t\n\f]*\\(.*$\\)" arg)
9469 (setq space-args (append space-args
9470 (list (match-string-no-properties 1 arg))))
9471 (setq arg (match-string 2 arg))))
9474 (setq arg (car space-args)
9475 space-args (cdr space-args))
9479 (setq next-param arg))
9481 (setq next-param arg))
9483 (setq next-param arg))
9484 ;; +libext+(ext1)+(ext2)...
9485 ((string-match "^\\+libext\\+\\(.*\\)" arg)
9486 (setq arg (match-string 1 arg))
9487 (while (string-match "\\([^+]+\\)\\+?\\(.*\\)" arg)
9488 (verilog-add-list-unique `verilog-library-extensions
9489 (match-string 1 arg))
9490 (setq arg (match-string 2 arg))))
9492 ((or (string-match "^-D\\([^+=]*\\)[+=]\\(.*\\)" arg) ; -Ddefine=val
9493 (string-match "^-D\\([^+=]*\\)\\(\\)" arg) ; -Ddefine
9494 (string-match "^\\+define\\([^+=]*\\)[+=]\\(.*\\)" arg) ; +define+val
9495 (string-match "^\\+define\\([^+=]*\\)\\(\\)" arg)) ; +define+define
9496 (verilog-set-define (match-string 1 arg) (match-string 2 arg)))
9498 ((or (string-match "^\\+incdir\\+\\(.*\\)" arg) ; +incdir+dir
9499 (string-match "^-I\\(.*\\)" arg)) ; -Idir
9500 (verilog-add-list-unique `verilog-library-directories
9501 (match-string 1 (substitute-in-file-name arg))))
9503 ((equal "+librescan" arg))
9504 ((string-match "^-U\\(.*\\)" arg)) ; -Udefine
9505 ;; Second parameters
9506 ((equal next-param "-f")
9507 (setq next-param nil)
9508 (verilog-getopt-file (substitute-in-file-name arg)))
9509 ((equal next-param "-v")
9510 (setq next-param nil)
9511 (verilog-add-list-unique `verilog-library-files
9512 (substitute-in-file-name arg)))
9513 ((equal next-param "-y")
9514 (setq next-param nil)
9515 (verilog-add-list-unique `verilog-library-directories
9516 (substitute-in-file-name arg)))
9518 ((string-match "^[^-+]" arg)
9519 (verilog-add-list-unique `verilog-library-files
9520 (substitute-in-file-name arg)))
9521 ;; Default - ignore; no warning
9523 ;;(verilog-getopt (list "+libext+.a+.b" "+incdir+foodir" "+define+a+aval" "-f" "otherf" "-v" "library" "-y" "dir"))
9525 (defun verilog-getopt-file (filename)
9526 "Read Verilog options from the specified FILENAME."
9528 (let ((fns (verilog-library-filenames filename (buffer-file-name)))
9529 (orig-buffer (current-buffer))
9532 (set-buffer (find-file-noselect (car fns)))
9533 (error "%s: Can't find verilog-getopt-file -f file: %s"
9534 (verilog-point-text) filename))
9535 (goto-char (point-min))
9537 (setq line (buffer-substring (point) (point-at-eol)))
9539 (when (string-match "//" line)
9540 (setq line (substring line 0 (match-beginning 0))))
9541 (with-current-buffer orig-buffer ; Variables are buffer-local, so need right context.
9542 (verilog-getopt line))))))
9544 (defun verilog-getopt-flags ()
9545 "Convert `verilog-library-flags' into standard library variables."
9546 ;; If the flags are local, then all the outputs should be local also
9547 (when (local-variable-p `verilog-library-flags (current-buffer))
9548 (mapc 'make-local-variable '(verilog-library-extensions
9549 verilog-library-directories
9550 verilog-library-files
9551 verilog-library-flags)))
9552 ;; Allow user to customize
9553 (verilog-run-hooks 'verilog-before-getopt-flags-hook)
9554 ;; Process arguments
9555 (verilog-getopt verilog-library-flags)
9556 ;; Allow user to customize
9557 (verilog-run-hooks 'verilog-getopt-flags-hook))
9559 (defun verilog-add-list-unique (varref object)
9560 "Append to VARREF list the given OBJECT,
9561 unless it is already a member of the variable's list."
9562 (unless (member object (symbol-value varref))
9563 (set varref (append (symbol-value varref) (list object))))
9565 ;;(progn (setq l '()) (verilog-add-list-unique `l "a") (verilog-add-list-unique `l "a") l)
9567 (defun verilog-current-flags ()
9568 "Convert `verilog-library-flags' and similar variables to command line.
9569 Used for __FLAGS__ in `verilog-expand-command'."
9570 (let ((cmd (mapconcat `concat verilog-library-flags " ")))
9571 (when (equal cmd "")
9573 "+libext+" (mapconcat `concat verilog-library-extensions "+")
9574 (mapconcat (lambda (i) (concat " -y " i " +incdir+" i))
9575 verilog-library-directories "")
9576 (mapconcat (lambda (i) (concat " -v " i))
9577 verilog-library-files ""))))
9579 ;;(verilog-current-flags)
9582 ;;; Cached directory support:
9585 (defvar verilog-dir-cache-preserving nil
9586 "If true, the directory cache is enabled, and file system changes are ignored.
9587 See `verilog-dir-exists-p' and `verilog-dir-files'.")
9589 ;; If adding new cached variable, add also to verilog-preserve-dir-cache
9590 (defvar verilog-dir-cache-list nil
9591 "Alist of (((Cwd Dirname) Results)...) for caching `verilog-dir-files'.")
9592 (defvar verilog-dir-cache-lib-filenames nil
9593 "Cached data for `verilog-library-filenames'.")
9595 (defmacro verilog-preserve-dir-cache (&rest body)
9596 "Execute the BODY forms, allowing directory cache preservation within BODY.
9597 This means that changes inside BODY made to the file system will not be
9598 seen by the `verilog-dir-files' and related functions."
9599 `(let ((verilog-dir-cache-preserving (current-buffer))
9600 verilog-dir-cache-list
9601 verilog-dir-cache-lib-filenames)
9604 (defun verilog-dir-files (dirname)
9605 "Return all filenames in the DIRNAME directory.
9606 Relative paths depend on the `default-directory'.
9607 Results are cached if inside `verilog-preserve-dir-cache'."
9608 (unless verilog-dir-cache-preserving
9609 (setq verilog-dir-cache-list nil)) ; Cache disabled
9610 ;; We don't use expand-file-name on the dirname to make key, as it's slow
9611 (let* ((cache-key (list dirname default-directory))
9612 (fass (assoc cache-key verilog-dir-cache-list))
9614 (cond (fass ; Return data from cache hit
9617 (setq exp-dirname (expand-file-name dirname)
9618 data (and (file-directory-p exp-dirname)
9619 (directory-files exp-dirname nil nil nil)))
9620 ;; Note we also encache nil for non-existing dirs.
9621 (setq verilog-dir-cache-list (cons (list cache-key data)
9622 verilog-dir-cache-list))
9624 ;; Miss-and-hit test:
9625 ;;(verilog-preserve-dir-cache (prin1 (verilog-dir-files "."))
9626 ;; (prin1 (verilog-dir-files ".")) nil)
9628 (defun verilog-dir-file-exists-p (filename)
9629 "Return true if FILENAME exists.
9630 Like `file-exists-p' but results are cached if inside
9631 `verilog-preserve-dir-cache'."
9632 (let* ((dirname (file-name-directory filename))
9633 ;; Correct for file-name-nondirectory returning same if no slash.
9634 (dirnamed (if (or (not dirname) (equal dirname filename))
9635 default-directory dirname))
9636 (flist (verilog-dir-files dirnamed)))
9638 (member (file-name-nondirectory filename) flist)
9640 ;;(verilog-dir-file-exists-p "verilog-mode.el")
9641 ;;(verilog-dir-file-exists-p "../verilog-mode/verilog-mode.el")
9644 ;;; Module name lookup:
9647 (defun verilog-module-inside-filename-p (module filename)
9648 "Return modi if MODULE is specified inside FILENAME, else nil.
9649 Allows version control to check out the file if need be."
9650 (and (or (file-exists-p filename)
9651 (and (fboundp 'vc-backend)
9652 (vc-backend filename)))
9654 (with-current-buffer (find-file-noselect filename)
9656 (goto-char (point-min))
9658 ;; It may be tempting to look for verilog-defun-re,
9659 ;; don't, it slows things down a lot!
9660 (verilog-re-search-forward-quick "\\<\\(module\\|interface\\|program\\)\\>" nil t)
9661 (setq type (match-string-no-properties 0))
9662 (verilog-re-search-forward-quick "[(;]" nil t))
9663 (if (equal module (verilog-read-module-name))
9664 (setq modi (verilog-modi-new module filename (point) type))))
9667 (defun verilog-is-number (symbol)
9668 "Return true if SYMBOL is number-like."
9669 (or (string-match "^[0-9 \t:]+$" symbol)
9670 (string-match "^[---]*[0-9]+$" symbol)
9671 (string-match "^[0-9 \t]+'s?[hdxbo][0-9a-fA-F_xz? \t]*$" symbol)))
9673 (defun verilog-symbol-detick (symbol wing-it)
9674 "Return an expanded SYMBOL name without any defines.
9675 If the variable vh-{symbol} is defined, return that value.
9676 If undefined, and WING-IT, return just SYMBOL without the tick, else nil."
9677 (while (and symbol (string-match "^`" symbol))
9678 (setq symbol (substring symbol 1))
9680 ;; Namespace intentionally short for AUTOs and compatibility
9681 (if (boundp (intern (concat "vh-" symbol)))
9682 ;; Emacs has a bug where boundp on a buffer-local
9683 ;; variable in only one buffer returns t in another.
9684 ;; This can confuse, so check for nil.
9685 ;; Namespace intentionally short for AUTOs and compatibility
9686 (let ((val (eval (intern (concat "vh-" symbol)))))
9688 (if wing-it symbol nil)
9690 (if wing-it symbol nil))))
9692 ;;(verilog-symbol-detick "`mod" nil)
9694 (defun verilog-symbol-detick-denumber (symbol)
9695 "Return SYMBOL with defines converted and any numbers dropped to nil."
9696 (when (string-match "^`" symbol)
9697 ;; This only will work if the define is a simple signal, not
9698 ;; something like a[b]. Sorry, it should be substituted into the parser
9700 (verilog-string-replace-matches
9701 "\\[[^0-9: \t]+\\]" "" nil nil
9702 (or (verilog-symbol-detick symbol nil)
9703 (if verilog-auto-sense-defines-constant
9706 (if (verilog-is-number symbol)
9710 (defun verilog-symbol-detick-text (text)
9711 "Return TEXT without any known defines.
9712 If the variable vh-{symbol} is defined, substitute that value."
9713 (let ((ok t) symbol val)
9714 (while (and ok (string-match "`\\([a-zA-Z0-9_]+\\)" text))
9715 (setq symbol (match-string 1 text))
9718 ;; Namespace intentionally short for AUTOs and compatibility
9719 (boundp (intern (concat "vh-" symbol)))
9720 ;; Emacs has a bug where boundp on a buffer-local
9721 ;; variable in only one buffer returns t in another.
9722 ;; This can confuse, so check for nil.
9723 ;; Namespace intentionally short for AUTOs and compatibility
9724 (setq val (eval (intern (concat "vh-" symbol)))))
9725 (setq text (replace-match val nil nil text)))
9726 (t (setq ok nil)))))
9728 ;;(progn (setq vh-mod "`foo" vh-foo "bar") (verilog-symbol-detick-text "bar `mod `undefed"))
9730 (defun verilog-expand-dirnames (&optional dirnames)
9731 "Return a list of existing directories given a list of wildcarded DIRNAMES.
9732 Or, just the existing dirnames themselves if there are no wildcards."
9733 ;; Note this function is performance critical.
9734 ;; Do not call anything that requires disk access that cannot be cached.
9737 (error "`verilog-library-directories' should include at least `.'"))
9738 (setq dirnames (reverse dirnames)) ; not nreverse
9740 pattern dirfile dirfiles dirname root filename rest basefile)
9742 (setq dirname (substitute-in-file-name (car dirnames))
9743 dirnames (cdr dirnames))
9744 (cond ((string-match (concat "^\\(\\|[/\\]*[^*?]*[/\\]\\)" ; root
9745 "\\([^/\\]*[*?][^/\\]*\\)" ; filename with *?
9748 (setq root (match-string 1 dirname)
9749 filename (match-string 2 dirname)
9750 rest (match-string 3 dirname)
9752 ;; now replace those * and ? with .+ and .
9753 ;; use ^ and /> to get only whole file names
9754 (setq pattern (verilog-string-replace-matches "[*]" ".+" nil nil pattern)
9755 pattern (verilog-string-replace-matches "[?]" "." nil nil pattern)
9756 pattern (concat "^" pattern "$")
9757 dirfiles (verilog-dir-files root))
9759 (setq basefile (car dirfiles)
9760 dirfile (expand-file-name (concat root basefile rest))
9761 dirfiles (cdr dirfiles))
9762 (if (and (string-match pattern basefile)
9763 ;; Don't allow abc/*/rtl to match abc/rtl via ..
9764 (not (equal basefile "."))
9765 (not (equal basefile ".."))
9766 (file-directory-p dirfile))
9767 (setq dirlist (cons dirfile dirlist)))))
9770 (if (file-directory-p dirname)
9771 (setq dirlist (cons dirname dirlist))))))
9773 ;;(verilog-expand-dirnames (list "." ".." "nonexist" "../*" "/home/wsnyder/*/v"))
9775 (defun verilog-library-filenames (filename &optional current check-ext)
9776 "Return a search path to find the given FILENAME or module name.
9777 Uses the optional CURRENT filename or variable `buffer-file-name', plus
9778 `verilog-library-directories' and `verilog-library-extensions'
9779 variables to build the path. With optional CHECK-EXT also check
9780 `verilog-library-extensions'."
9781 (unless current (setq current (buffer-file-name)))
9782 (unless verilog-dir-cache-preserving
9783 (setq verilog-dir-cache-lib-filenames nil))
9784 (let* ((cache-key (list filename current check-ext))
9785 (fass (assoc cache-key verilog-dir-cache-lib-filenames))
9786 chkdirs chkdir chkexts fn outlist)
9787 (cond (fass ; Return data from cache hit
9790 ;; Note this expand can't be easily cached, as we need to
9791 ;; pick up buffer-local variables for newly read sub-module files
9792 (setq chkdirs (verilog-expand-dirnames verilog-library-directories))
9794 (setq chkdir (expand-file-name (car chkdirs)
9795 (file-name-directory current))
9796 chkexts (if check-ext verilog-library-extensions `("")))
9798 (setq fn (expand-file-name (concat filename (car chkexts))
9800 ;;(message "Check for %s" fn)
9801 (if (verilog-dir-file-exists-p fn)
9802 (setq outlist (cons (expand-file-name
9803 fn (file-name-directory current))
9805 (setq chkexts (cdr chkexts)))
9806 (setq chkdirs (cdr chkdirs)))
9807 (setq outlist (nreverse outlist))
9808 (setq verilog-dir-cache-lib-filenames
9809 (cons (list cache-key outlist)
9810 verilog-dir-cache-lib-filenames))
9813 (defun verilog-module-filenames (module current)
9814 "Return a search path to find the given MODULE name.
9815 Uses the CURRENT filename, `verilog-library-extensions',
9816 `verilog-library-directories' and `verilog-library-files'
9817 variables to build the path."
9818 ;; Return search locations for it
9819 (append (list current) ; first, current buffer
9820 (verilog-library-filenames module current t)
9821 verilog-library-files)) ; finally, any libraries
9824 ;; Module Information
9826 ;; Many of these functions work on "modi" a module information structure
9827 ;; A modi is: [module-name-string file-name begin-point]
9829 (defvar verilog-cache-enabled t
9830 "Non-nil enables caching of signals, etc. Set to nil for debugging to make things SLOW!")
9832 (defvar verilog-modi-cache-list nil
9833 "Cache of ((Module Function) Buf-Tick Buf-Modtime Func-Returns)...
9834 For speeding up verilog-modi-get-* commands.
9836 (make-variable-buffer-local 'verilog-modi-cache-list)
9838 (defvar verilog-modi-cache-preserve-tick nil
9839 "Modification tick after which the cache is still considered valid.
9840 Use `verilog-preserve-modi-cache' to set it.")
9841 (defvar verilog-modi-cache-preserve-buffer nil
9842 "Modification tick after which the cache is still considered valid.
9843 Use `verilog-preserve-modi-cache' to set it.")
9844 (defvar verilog-modi-cache-current-enable nil
9845 "Non-nil means allow caching `verilog-modi-current', set by let().")
9846 (defvar verilog-modi-cache-current nil
9847 "Currently active `verilog-modi-current', if any, set by let().")
9848 (defvar verilog-modi-cache-current-max nil
9849 "Current endmodule point for `verilog-modi-cache-current', if any.")
9851 (defun verilog-modi-current ()
9852 "Return the modi structure for the module currently at point, possibly cached."
9853 (cond ((and verilog-modi-cache-current
9854 (>= (point) (verilog-modi-get-point verilog-modi-cache-current))
9855 (<= (point) verilog-modi-cache-current-max))
9856 ;; Slow assertion, for debugging the cache:
9857 ;;(or (equal verilog-modi-cache-current (verilog-modi-current-get)) (debug))
9858 verilog-modi-cache-current)
9859 (verilog-modi-cache-current-enable
9860 (setq verilog-modi-cache-current (verilog-modi-current-get)
9861 verilog-modi-cache-current-max
9862 ;; The cache expires when we pass "endmodule" as then the
9863 ;; current modi may change to the next module
9864 ;; This relies on the AUTOs generally inserting, not deleting text
9866 (verilog-re-search-forward-quick verilog-end-defun-re nil nil)))
9867 verilog-modi-cache-current)
9869 (verilog-modi-current-get))))
9871 (defun verilog-modi-current-get ()
9872 "Return the modi structure for the module currently at point."
9873 (let* (name type pt)
9874 ;; read current module's name
9876 (verilog-re-search-backward-quick verilog-defun-re nil nil)
9877 (setq type (match-string-no-properties 0))
9878 (verilog-re-search-forward-quick "(" nil nil)
9879 (setq name (verilog-read-module-name))
9881 ;; return modi - note this vector built two places
9882 (verilog-modi-new name (or (buffer-file-name) (current-buffer)) pt type)))
9884 (defvar verilog-modi-lookup-cache nil "Hash of (modulename modi).")
9885 (make-variable-buffer-local 'verilog-modi-lookup-cache)
9886 (defvar verilog-modi-lookup-last-current nil "Cache of `current-buffer' at last lookup.")
9887 (defvar verilog-modi-lookup-last-tick nil "Cache of `buffer-chars-modified-tick' at last lookup.")
9889 (defun verilog-modi-lookup (module allow-cache &optional ignore-error)
9890 "Find the file and point at which MODULE is defined.
9891 If ALLOW-CACHE is set, check and remember cache of previous lookups.
9892 Return modi if successful, else print message unless IGNORE-ERROR is true."
9893 (let* ((current (or (buffer-file-name) (current-buffer)))
9896 ;;(message "verilog-modi-lookup: %s" module)
9897 (cond ((and verilog-modi-lookup-cache
9898 verilog-cache-enabled
9900 (setq modi (gethash module verilog-modi-lookup-cache))
9901 (equal verilog-modi-lookup-last-current current)
9902 ;; If hit is in current buffer, then tick must match
9903 (or (equal verilog-modi-lookup-last-tick (buffer-chars-modified-tick))
9904 (not (equal current (verilog-modi-file-or-buffer modi)))))
9905 ;;(message "verilog-modi-lookup: HIT %S" modi)
9908 (t (let* ((realname (verilog-symbol-detick module t))
9909 (orig-filenames (verilog-module-filenames realname current))
9910 (filenames orig-filenames)
9912 (while (and filenames (not mif))
9913 (if (not (setq mif (verilog-module-inside-filename-p realname (car filenames))))
9914 (setq filenames (cdr filenames))))
9915 ;; mif has correct form to become later elements of modi
9917 (or mif ignore-error
9920 "%s: Can't locate `%s' module definition%s"
9921 "\n Check the verilog-library-directories variable."
9922 "\n I looked in (if not listed, doesn't exist):\n\t%s")
9923 (verilog-point-text) module
9924 (if (not (equal module realname))
9925 (concat " (Expanded macro to " realname ")")
9927 (mapconcat 'concat orig-filenames "\n\t")))
9928 (when (eval-when-compile (fboundp 'make-hash-table))
9929 (unless verilog-modi-lookup-cache
9930 (setq verilog-modi-lookup-cache
9931 (make-hash-table :test 'equal :rehash-size 4.0)))
9932 (puthash module modi verilog-modi-lookup-cache))
9933 (setq verilog-modi-lookup-last-current current
9934 verilog-modi-lookup-last-tick (buffer-chars-modified-tick)))))
9937 (defun verilog-modi-filename (modi)
9938 "Filename of MODI, or name of buffer if it's never been saved."
9939 (if (bufferp (verilog-modi-file-or-buffer modi))
9940 (or (buffer-file-name (verilog-modi-file-or-buffer modi))
9941 (buffer-name (verilog-modi-file-or-buffer modi)))
9942 (verilog-modi-file-or-buffer modi)))
9944 (defun verilog-modi-goto (modi)
9945 "Move point/buffer to specified MODI."
9946 (or modi (error "Passed unfound modi to goto, check earlier"))
9947 (set-buffer (if (bufferp (verilog-modi-file-or-buffer modi))
9948 (verilog-modi-file-or-buffer modi)
9949 (find-file-noselect (verilog-modi-file-or-buffer modi))))
9950 (or (equal major-mode `verilog-mode) ; Put into Verilog mode to get syntax
9952 (goto-char (verilog-modi-get-point modi)))
9954 (defun verilog-goto-defun-file (module)
9955 "Move point to the file at which a given MODULE is defined."
9956 (interactive "sGoto File for Module: ")
9957 (let* ((modi (verilog-modi-lookup module nil)))
9959 (verilog-modi-goto modi)
9960 (switch-to-buffer (current-buffer)))))
9962 (defun verilog-modi-cache-results (modi function)
9963 "Run on MODI the given FUNCTION. Locate the module in a file.
9964 Cache the output of function so next call may have faster access."
9966 (save-excursion ; Cache is buffer-local so can't avoid this.
9967 (verilog-modi-goto modi)
9968 (if (and (setq fass (assoc (list modi function)
9969 verilog-modi-cache-list))
9970 ;; Destroy caching when incorrect; Modified or file changed
9971 (not (and verilog-cache-enabled
9972 (or (equal (buffer-chars-modified-tick) (nth 1 fass))
9973 (and verilog-modi-cache-preserve-tick
9974 (<= verilog-modi-cache-preserve-tick (nth 1 fass))
9975 (equal verilog-modi-cache-preserve-buffer (current-buffer))))
9976 (equal (visited-file-modtime) (nth 2 fass)))))
9977 (setq verilog-modi-cache-list nil
9980 ;; Return data from cache hit
9984 ;; Clear then restore any highlighting to make emacs19 happy
9986 (verilog-save-font-no-change-functions
9987 (funcall function))))
9988 ;; Cache for next time
9989 (setq verilog-modi-cache-list
9990 (cons (list (list modi function)
9991 (buffer-chars-modified-tick)
9992 (visited-file-modtime)
9994 verilog-modi-cache-list))
9997 (defun verilog-modi-cache-add (modi function element sig-list)
9998 "Add function return results to the module cache.
9999 Update MODI's cache for given FUNCTION so that the return ELEMENT of that
10000 function now contains the additional SIG-LIST parameters."
10003 (verilog-modi-goto modi)
10004 (if (setq fass (assoc (list modi function)
10005 verilog-modi-cache-list))
10006 (let ((func-returns (nth 3 fass)))
10007 (aset func-returns element
10008 (append sig-list (aref func-returns element))))))))
10010 (defmacro verilog-preserve-modi-cache (&rest body)
10011 "Execute the BODY forms, allowing cache preservation within BODY.
10012 This means that changes to the buffer will not result in the cache being
10013 flushed. If the changes affect the modsig state, they must call the
10014 modsig-cache-add-* function, else the results of later calls may be
10015 incorrect. Without this, changes are assumed to be adding/removing signals
10016 and invalidating the cache."
10017 `(let ((verilog-modi-cache-preserve-tick (buffer-chars-modified-tick))
10018 (verilog-modi-cache-preserve-buffer (current-buffer)))
10022 (defun verilog-modi-modport-lookup-one (modi name &optional ignore-error)
10023 "Given a MODI, return the declarations related to the given modport NAME.
10024 Report errors unless optional IGNORE-ERROR."
10025 ;; Recursive routine - see below
10026 (let* ((realname (verilog-symbol-detick name t))
10027 (modport (assoc name (verilog-decls-get-modports (verilog-modi-get-decls modi)))))
10028 (or modport ignore-error
10029 (error "%s: Can't locate `%s' modport definition%s"
10030 (verilog-point-text) name
10031 (if (not (equal name realname))
10032 (concat " (Expanded macro to " realname ")")
10034 (let* ((decls (verilog-modport-decls modport))
10035 (clks (verilog-modport-clockings modport)))
10036 ;; Now expand any clocking's
10038 (setq decls (verilog-decls-append
10040 (verilog-modi-modport-lookup-one modi (car clks) ignore-error)))
10041 (setq clks (cdr clks)))
10044 (defun verilog-modi-modport-lookup (modi name-re &optional ignore-error)
10045 "Given a MODI, return the declarations related to the given modport NAME-RE.
10046 If the modport points to any clocking blocks, expand the signals to include
10047 those clocking block's signals."
10048 ;; Recursive routine - see below
10049 (let* ((mod-decls (verilog-modi-get-decls modi))
10050 (clks (verilog-decls-get-modports mod-decls))
10051 (name-re (concat "^" name-re "$"))
10052 (decls (verilog-decls-new nil nil nil nil nil nil nil nil nil)))
10053 ;; Pull in all modports
10055 (when (string-match name-re (verilog-modport-name (car clks)))
10056 (setq decls (verilog-decls-append
10058 (verilog-modi-modport-lookup-one modi (verilog-modport-name (car clks)) ignore-error))))
10059 (setq clks (cdr clks)))
10062 (defun verilog-signals-matching-enum (in-list enum)
10063 "Return all signals in IN-LIST matching the given ENUM."
10066 (if (equal (verilog-sig-enum (car in-list)) enum)
10067 (setq out-list (cons (car in-list) out-list)))
10068 (setq in-list (cdr in-list)))
10070 ;; Namespace intentionally short for AUTOs and compatibility
10071 (let* ((enumvar (intern (concat "venum-" enum)))
10072 (enumlist (and (boundp enumvar) (eval enumvar))))
10074 (add-to-list 'out-list (list (car enumlist)))
10075 (setq enumlist (cdr enumlist))))
10076 (nreverse out-list)))
10078 (defun verilog-signals-matching-regexp (in-list regexp)
10079 "Return all signals in IN-LIST matching the given REGEXP, if non-nil."
10080 (if (or (not regexp) (equal regexp ""))
10082 (let ((case-fold-search verilog-case-fold)
10085 (if (string-match regexp (verilog-sig-name (car in-list)))
10086 (setq out-list (cons (car in-list) out-list)))
10087 (setq in-list (cdr in-list)))
10088 (nreverse out-list))))
10090 (defun verilog-signals-not-matching-regexp (in-list regexp)
10091 "Return all signals in IN-LIST not matching the given REGEXP, if non-nil."
10092 (if (or (not regexp) (equal regexp ""))
10094 (let ((case-fold-search verilog-case-fold)
10097 (if (not (string-match regexp (verilog-sig-name (car in-list))))
10098 (setq out-list (cons (car in-list) out-list)))
10099 (setq in-list (cdr in-list)))
10100 (nreverse out-list))))
10102 (defun verilog-signals-matching-dir-re (in-list decl-type regexp)
10103 "Return all signals in IN-LIST matching the given DECL-TYPE and REGEXP,
10105 (if (or (not regexp) (equal regexp ""))
10107 (let (out-list to-match)
10109 ;; Note verilog-insert-one-definition matches on this order
10110 (setq to-match (concat
10112 " " (verilog-sig-signed (car in-list))
10113 " " (verilog-sig-multidim (car in-list))
10114 (verilog-sig-bits (car in-list))))
10115 (if (string-match regexp to-match)
10116 (setq out-list (cons (car in-list) out-list)))
10117 (setq in-list (cdr in-list)))
10118 (nreverse out-list))))
10120 (defun verilog-signals-edit-wire-reg (in-list)
10121 "Return all signals in IN-LIST with wire/reg data types made blank."
10122 (mapcar (lambda (sig)
10123 (when (member (verilog-sig-type sig) '("wire" "reg"))
10124 (verilog-sig-type-set sig nil))
10128 (defun verilog-decls-get-signals (decls)
10129 "Return all declared signals in DECLS, excluding `assign' statements."
10131 (verilog-decls-get-outputs decls)
10132 (verilog-decls-get-inouts decls)
10133 (verilog-decls-get-inputs decls)
10134 (verilog-decls-get-vars decls)
10135 (verilog-decls-get-consts decls)
10136 (verilog-decls-get-gparams decls)))
10138 (defun verilog-decls-get-ports (decls)
10140 (verilog-decls-get-outputs decls)
10141 (verilog-decls-get-inouts decls)
10142 (verilog-decls-get-inputs decls)))
10144 (defun verilog-decls-get-iovars (decls)
10146 (verilog-decls-get-vars decls)
10147 (verilog-decls-get-outputs decls)
10148 (verilog-decls-get-inouts decls)
10149 (verilog-decls-get-inputs decls)))
10151 (defsubst verilog-modi-cache-add-outputs (modi sig-list)
10152 (verilog-modi-cache-add modi 'verilog-read-decls 0 sig-list))
10153 (defsubst verilog-modi-cache-add-inouts (modi sig-list)
10154 (verilog-modi-cache-add modi 'verilog-read-decls 1 sig-list))
10155 (defsubst verilog-modi-cache-add-inputs (modi sig-list)
10156 (verilog-modi-cache-add modi 'verilog-read-decls 2 sig-list))
10157 (defsubst verilog-modi-cache-add-vars (modi sig-list)
10158 (verilog-modi-cache-add modi 'verilog-read-decls 3 sig-list))
10159 (defsubst verilog-modi-cache-add-gparams (modi sig-list)
10160 (verilog-modi-cache-add modi 'verilog-read-decls 7 sig-list))
10163 ;;; Auto creation utilities:
10166 (defun verilog-auto-re-search-do (search-for func)
10167 "Search for the given auto text regexp SEARCH-FOR, and perform FUNC where it occurs."
10168 (goto-char (point-min))
10169 (while (verilog-re-search-forward-quick search-for nil t)
10172 (defun verilog-insert-one-definition (sig type indent-pt)
10173 "Print out a definition for SIG of the given TYPE,
10174 with appropriate INDENT-PT indentation."
10175 (indent-to indent-pt)
10176 ;; Note verilog-signals-matching-dir-re matches on this order
10178 (when (verilog-sig-modport sig)
10179 (insert "." (verilog-sig-modport sig)))
10180 (when (verilog-sig-signed sig)
10181 (insert " " (verilog-sig-signed sig)))
10182 (when (verilog-sig-multidim sig)
10183 (insert " " (verilog-sig-multidim-string sig)))
10184 (when (verilog-sig-bits sig)
10185 (insert " " (verilog-sig-bits sig)))
10186 (indent-to (max 24 (+ indent-pt 16)))
10187 (unless (= (char-syntax (preceding-char)) ?\ )
10188 (insert " ")) ; Need space between "]name" if indent-to did nothing
10189 (insert (verilog-sig-name sig))
10190 (when (verilog-sig-memory sig)
10191 (insert " " (verilog-sig-memory sig))))
10193 (defun verilog-insert-definition (modi sigs direction indent-pt v2k &optional dont-sort)
10194 "Print out a definition for MODI's list of SIGS of the given DIRECTION,
10195 with appropriate INDENT-PT indentation. If V2K, use Verilog 2001 I/O
10196 format. Sort unless DONT-SORT. DIRECTION is normally wire/reg/output.
10197 When MODI is non-null, also add to modi-cache, for tracking."
10199 (cond ((equal direction "wire")
10200 (verilog-modi-cache-add-vars modi sigs))
10201 ((equal direction "reg")
10202 (verilog-modi-cache-add-vars modi sigs))
10203 ((equal direction "output")
10204 (verilog-modi-cache-add-outputs modi sigs)
10205 (when verilog-auto-declare-nettype
10206 (verilog-modi-cache-add-vars modi sigs)))
10207 ((equal direction "input")
10208 (verilog-modi-cache-add-inputs modi sigs)
10209 (when verilog-auto-declare-nettype
10210 (verilog-modi-cache-add-vars modi sigs)))
10211 ((equal direction "inout")
10212 (verilog-modi-cache-add-inouts modi sigs)
10213 (when verilog-auto-declare-nettype
10214 (verilog-modi-cache-add-vars modi sigs)))
10215 ((equal direction "interface"))
10216 ((equal direction "parameter")
10217 (verilog-modi-cache-add-gparams modi sigs))
10219 (error "Unsupported verilog-insert-definition direction: `%s'" direction))))
10221 (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
10223 (let ((sig (car sigs)))
10224 (verilog-insert-one-definition
10226 ;; Want "type x" or "output type x", not "wire type x"
10227 (cond ((or (verilog-sig-type sig)
10228 verilog-auto-wire-type)
10230 (when (member direction '("input" "output" "inout"))
10231 (concat direction " "))
10232 (or (verilog-sig-type sig)
10233 verilog-auto-wire-type)))
10234 ((and verilog-auto-declare-nettype
10235 (member direction '("input" "output" "inout")))
10236 (concat direction " " verilog-auto-declare-nettype))
10240 (insert (if v2k "," ";"))
10241 (if (or (not (verilog-sig-comment sig))
10242 (equal "" (verilog-sig-comment sig)))
10244 (indent-to (max 48 (+ indent-pt 40)))
10245 (verilog-insert "// " (verilog-sig-comment sig) "\n"))
10246 (setq sigs (cdr sigs)))))
10249 (if (not (boundp 'indent-pt))
10250 (defvar indent-pt nil "Local used by `verilog-insert-indent'.")))
10252 (defun verilog-insert-indent (&rest stuff)
10253 "Indent to position stored in local `indent-pt' variable, then insert STUFF.
10254 Presumes that any newlines end a list element."
10255 (let ((need-indent t))
10257 (if need-indent (indent-to indent-pt))
10258 (setq need-indent nil)
10259 (verilog-insert (car stuff))
10260 (setq need-indent (string-match "\n$" (car stuff))
10261 stuff (cdr stuff)))))
10262 ;;(let ((indent-pt 10)) (verilog-insert-indent "hello\n" "addon" "there\n"))
10264 (defun verilog-forward-or-insert-line ()
10265 "Move forward a line, unless at EOB, then insert a newline."
10266 (if (eobp) (insert "\n")
10269 (defun verilog-repair-open-comma ()
10270 "Insert comma if previous argument is other than an open parenthesis or endif."
10271 ;; We can't just search backward for ) as it might be inside another expression.
10272 ;; Also want "`ifdef X input foo `endif" to just leave things to the human to deal with
10274 (verilog-backward-syntactic-ws-quick)
10275 (when (and (not (save-excursion ; Not beginning (, or existing ,
10277 (looking-at "[(,]")))
10278 (not (save-excursion ; Not `endif, or user define
10280 (skip-chars-backward "[a-zA-Z0-9_`]")
10281 (looking-at "`"))))
10284 (defun verilog-repair-close-comma ()
10285 "If point is at a comma followed by a close parenthesis, fix it.
10286 This repairs those mis-inserted by an AUTOARG."
10287 ;; It would be much nicer if Verilog allowed extra commas like Perl does!
10289 (verilog-forward-close-paren)
10291 (verilog-backward-syntactic-ws-quick)
10293 (when (looking-at ",")
10296 (defun verilog-make-width-expression (range-exp)
10297 "Return an expression calculating the length of a range [x:y] in RANGE-EXP."
10298 ;; strip off the []
10299 (cond ((not range-exp)
10302 (if (string-match "^\\[\\(.*\\)\\]$" range-exp)
10303 (setq range-exp (match-string 1 range-exp)))
10304 (cond ((not range-exp)
10306 ;; [#:#] We can compute a numeric result
10307 ((string-match "^\\s *\\([0-9]+\\)\\s *:\\s *\\([0-9]+\\)\\s *$"
10310 (1+ (abs (- (string-to-number (match-string 1 range-exp))
10311 (string-to-number (match-string 2 range-exp)))))))
10312 ;; [PARAM-1:0] can just return PARAM
10313 ((string-match "^\\s *\\([a-zA-Z_][a-zA-Z0-9_]*\\)\\s *-\\s *1\\s *:\\s *0\\s *$" range-exp)
10314 (match-string 1 range-exp))
10315 ;; [arbitrary] need math
10316 ((string-match "^\\(.*\\)\\s *:\\s *\\(.*\\)\\s *$" range-exp)
10317 (concat "(1+(" (match-string 1 range-exp) ")"
10318 (if (equal "0" (match-string 2 range-exp))
10319 "" ; Don't bother with -(0)
10320 (concat "-(" (match-string 2 range-exp) ")"))
10323 ;;(verilog-make-width-expression "`A:`B")
10325 (defun verilog-simplify-range-expression (expr)
10326 "Return a simplified range expression with constants eliminated from EXPR."
10327 ;; Note this is always called with brackets; ie [z] or [z:z]
10328 (if (not (string-match "[---+*()]" expr))
10329 expr ; short-circuit
10332 (while (not (equal last-pass out))
10333 (setq last-pass out)
10334 ;; Prefix regexp needs beginning of match, or some symbol of
10335 ;; lesser or equal precedence. We assume the [:]'s exist in expr.
10337 (while (string-match
10338 (concat "\\([[({:*+-]\\)" ; - must be last
10339 "(\\<\\([0-9A-Za-z_]+\\))"
10342 (setq out (replace-match "\\1\\2\\3" nil nil out)))
10343 (while (string-match
10344 (concat "\\([[({:*+-]\\)" ; - must be last
10345 "\\$clog2\\s *(\\<\\([0-9]+\\))"
10348 (setq out (replace-match
10350 (match-string 1 out)
10351 (int-to-string (verilog-clog2 (string-to-number (match-string 2 out))))
10352 (match-string 3 out))
10354 ;; For precedence do * before +/-
10355 (while (string-match
10356 (concat "\\([[({:*+-]\\)"
10357 "\\([0-9]+\\)\\s *\\([*]\\)\\s *\\([0-9]+\\)"
10360 (setq out (replace-match
10361 (concat (match-string 1 out)
10362 (int-to-string (* (string-to-number (match-string 2 out))
10363 (string-to-number (match-string 4 out))))
10364 (match-string 5 out))
10366 (while (string-match
10367 (concat "\\([[({:+-]\\)" ; No * here as higher prec
10368 "\\([0-9]+\\)\\s *\\([---+]\\)\\s *\\([0-9]+\\)"
10371 (let ((pre (match-string 1 out))
10372 (lhs (string-to-number (match-string 2 out)))
10373 (rhs (string-to-number (match-string 4 out)))
10374 (post (match-string 5 out))
10376 (when (equal pre "-")
10377 (setq lhs (- lhs)))
10378 (setq val (if (equal (match-string 3 out) "-")
10382 (concat (if (and (equal pre "-")
10384 "" ; Not "--20" but just "-20"
10386 (int-to-string val)
10391 ;;(verilog-simplify-range-expression "[1:3]") ; 1
10392 ;;(verilog-simplify-range-expression "[(1):3]") ; 1
10393 ;;(verilog-simplify-range-expression "[(((16)+1)+1+(1+1))]") ; 20
10394 ;;(verilog-simplify-range-expression "[(2*3+6*7)]") ; 48
10395 ;;(verilog-simplify-range-expression "[(FOO*4-1*2)]") ; FOO*4-2
10396 ;;(verilog-simplify-range-expression "[(FOO*4+1-1)]") ; FOO*4+0
10397 ;;(verilog-simplify-range-expression "[(func(BAR))]") ; func(BAR)
10398 ;;(verilog-simplify-range-expression "[FOO-1+1-1+1]") ; FOO-0
10399 ;;(verilog-simplify-range-expression "[$clog2(2)]") ; 1
10400 ;;(verilog-simplify-range-expression "[$clog2(7)]") ; 3
10402 (defun verilog-clog2 (value)
10403 "Compute $clog2 - ceiling log2 of VALUE."
10406 (ceiling (/ (log value) (log 2)))))
10408 (defun verilog-typedef-name-p (variable-name)
10409 "Return true if the VARIABLE-NAME is a type definition."
10410 (when verilog-typedef-regexp
10411 (verilog-string-match-fold verilog-typedef-regexp variable-name)))
10416 (defun verilog-delete-autos-lined ()
10417 "Delete autos that occupy multiple lines, between begin and end comments."
10418 ;; The newline must not have a comment property, so we must
10419 ;; delete the end auto's newline, not the first newline
10421 (let ((pt (point)))
10423 (looking-at "\\s-*// Beginning")
10424 (search-forward "// End of automatic" nil t))
10428 (delete-region pt (point)))))
10430 (defun verilog-delete-empty-auto-pair ()
10431 "Delete begin/end auto pair at point, if empty."
10433 (when (looking-at (concat "\\s-*// Beginning of automatic.*\n"
10434 "\\s-*// End of automatics\n"))
10435 (delete-region (point) (save-excursion (forward-line 2) (point)))))
10437 (defun verilog-forward-close-paren ()
10438 "Find the close parenthesis that match the current point.
10439 Ignore other close parenthesis with matching open parens."
10441 (while (> parens 0)
10442 (unless (verilog-re-search-forward-quick "[()]" nil t)
10443 (error "%s: Mismatching ()" (verilog-point-text)))
10444 (cond ((= (preceding-char) ?\( )
10445 (setq parens (1+ parens)))
10446 ((= (preceding-char) ?\) )
10447 (setq parens (1- parens)))))))
10449 (defun verilog-backward-open-paren ()
10450 "Find the open parenthesis that match the current point.
10451 Ignore other open parenthesis with matching close parens."
10453 (while (> parens 0)
10454 (unless (verilog-re-search-backward-quick "[()]" nil t)
10455 (error "%s: Mismatching ()" (verilog-point-text)))
10456 (cond ((= (following-char) ?\) )
10457 (setq parens (1+ parens)))
10458 ((= (following-char) ?\( )
10459 (setq parens (1- parens)))))))
10461 (defun verilog-backward-open-bracket ()
10462 "Find the open bracket that match the current point.
10463 Ignore other open bracket with matching close bracket."
10465 (while (> parens 0)
10466 (unless (verilog-re-search-backward-quick "[][]" nil t)
10467 (error "%s: Mismatching []" (verilog-point-text)))
10468 (cond ((= (following-char) ?\] )
10469 (setq parens (1+ parens)))
10470 ((= (following-char) ?\[ )
10471 (setq parens (1- parens)))))))
10473 (defun verilog-delete-to-paren ()
10474 "Delete the automatic inst/sense/arg created by autos.
10475 Deletion stops at the matching end parenthesis, outside comments."
10476 (delete-region (point)
10478 (verilog-backward-open-paren)
10479 (verilog-forward-sexp-ign-cmt 1) ; Moves to paren that closes argdecl's
10483 (defun verilog-auto-star-safe ()
10484 "Return if a .* AUTOINST is safe to delete or expand.
10485 It was created by the AUTOS themselves, or by the user."
10486 (and verilog-auto-star-expand
10488 (concat "[ \t\n\f,]*\\([)]\\|// " verilog-inst-comment-re "\\)"))))
10490 (defun verilog-delete-auto-star-all ()
10491 "Delete a .* AUTOINST, if it is safe."
10492 (when (verilog-auto-star-safe)
10493 (verilog-delete-to-paren)))
10495 (defun verilog-delete-auto-star-implicit ()
10496 "Delete all .* implicit connections created by `verilog-auto-star'.
10497 This function will be called automatically at save unless
10498 `verilog-auto-star-save' is set, any non-templated expanded pins will be
10501 (let (paren-pt indent have-close-paren)
10503 (goto-char (point-min))
10504 ;; We need to match these even outside of comments.
10505 ;; For reasonable performance, we don't check if inside comments, sorry.
10506 (while (re-search-forward "// Implicit \\.\\*" nil t)
10507 (setq paren-pt (point))
10508 (beginning-of-line)
10509 (setq have-close-paren
10511 (when (search-forward ");" paren-pt t)
10512 (setq indent (current-indentation))
10514 (delete-region (point) (+ 1 paren-pt)) ; Nuke line incl CR
10515 (when have-close-paren
10516 ;; Delete extra commentary
10520 (looking-at (concat "\\s *//\\s *" verilog-inst-comment-re "\n")))
10521 (delete-region (match-beginning 0) (match-end 0))))
10522 ;; If it is simple, we can put the ); on the same line as the last text
10523 (let ((rtn-pt (point)))
10525 (while (progn (backward-char 1)
10526 (looking-at "[ \t\n\f]")))
10527 (when (looking-at ",")
10528 (delete-region (+ 1 (point)) rtn-pt))))
10530 (indent-to indent))
10532 ;; Still need to kill final comma - always is one as we put one after the .*
10533 (re-search-backward ",")
10534 (delete-char 1))))))
10536 (defun verilog-delete-auto-buffer ()
10537 "Perform `verilog-delete-auto' on the current buffer.
10538 Intended for internal use inside a `verilog-save-font-no-change-functions' block."
10539 ;; Allow user to customize
10540 (verilog-run-hooks 'verilog-before-delete-auto-hook)
10542 ;; Remove those that have multi-line insertions, possibly with parameters
10543 ;; We allow anything beginning with AUTO, so that users can add their own
10545 (verilog-auto-re-search-do
10546 (concat "/\\*AUTO[A-Za-z0-9_]+"
10547 ;; Optional parens or quoted parameter or .* for (((...)))
10548 "\\(\\|([^)]*)\\|(\"[^\"]*\")\\).*?"
10550 'verilog-delete-autos-lined)
10551 ;; Remove those that are in parenthesis
10552 (verilog-auto-re-search-do
10555 (verilog-regexp-words
10556 `("AS" "AUTOARG" "AUTOCONCATWIDTH" "AUTOINST" "AUTOINSTPARAM"
10559 'verilog-delete-to-paren)
10560 ;; Do .* instantiations, but avoid removing any user pins by looking for our magic comments
10561 (verilog-auto-re-search-do "\\.\\*"
10562 'verilog-delete-auto-star-all)
10563 ;; Remove template comments ... anywhere in case was pasted after AUTOINST removed
10564 (goto-char (point-min))
10565 (while (re-search-forward "\\s-*// \\(Templated\\|Implicit \\.\\*\\)\\([ \tLT0-9]*\\| LHS: .*\\)?$" nil t)
10566 (replace-match ""))
10569 (verilog-run-hooks 'verilog-delete-auto-hook))
10571 (defun verilog-delete-auto ()
10572 "Delete the automatic outputs, regs, and wires created by \\[verilog-auto].
10573 Use \\[verilog-auto] to re-insert the updated AUTOs.
10575 The hooks `verilog-before-delete-auto-hook' and `verilog-delete-auto-hook' are
10576 called before and after this function, respectively."
10579 (if (buffer-file-name)
10580 (find-file-noselect (buffer-file-name))) ; To check we have latest version
10581 (verilog-save-font-no-change-functions
10582 (verilog-save-scan-cache
10583 (verilog-delete-auto-buffer)))))
10589 (defun verilog-inject-auto ()
10590 "Examine legacy non-AUTO code and insert AUTOs in appropriate places.
10592 Any always @ blocks with sensitivity lists that match computed lists will
10593 be replaced with /*AS*/ comments.
10595 Any cells will get /*AUTOINST*/ added to the end of the pin list.
10596 Pins with have identical names will be deleted.
10598 Argument lists will not be deleted, /*AUTOARG*/ will only be inserted to
10599 support adding new ports. You may wish to delete older ports yourself.
10603 module ExampInject (i, o);
10609 InstModule instName
10614 Typing \\[verilog-inject-auto] will make this into:
10616 module ExampInject (i, o/*AUTOARG*/
10621 always @ (/*AS*/i or j)
10623 InstModule instName
10632 (defun verilog-inject-arg ()
10633 "Inject AUTOARG into new code. See `verilog-inject-auto'."
10634 ;; Presume one module per file.
10636 (goto-char (point-min))
10637 (while (verilog-re-search-forward-quick "\\<module\\>" nil t)
10638 (let ((endmodp (save-excursion
10639 (verilog-re-search-forward-quick "\\<endmodule\\>" nil t)
10641 ;; See if there's already a comment .. inside a comment so not verilog-re-search
10642 (when (not (re-search-forward "/\\*AUTOARG\\*/" endmodp t))
10643 (verilog-re-search-forward-quick ";" nil t)
10645 (verilog-backward-syntactic-ws-quick)
10646 (backward-char 1) ; Moves to paren that closes argdecl's
10647 (when (looking-at ")")
10648 (verilog-insert "/*AUTOARG*/")))))))
10650 (defun verilog-inject-sense ()
10651 "Inject AUTOSENSE into new code. See `verilog-inject-auto'."
10653 (goto-char (point-min))
10654 (while (verilog-re-search-forward-quick "\\<always\\s *@\\s *(" nil t)
10655 (let* ((start-pt (point))
10656 (modi (verilog-modi-current))
10657 (moddecls (verilog-modi-get-decls modi))
10661 (verilog-forward-sexp-ign-cmt 1)
10662 (backward-char 1) ; End )
10663 (when (not (verilog-re-search-backward-quick "/\\*\\(AUTOSENSE\\|AS\\)\\*/" start-pt t))
10664 (setq pre-sigs (verilog-signals-from-signame
10665 (verilog-read-signals start-pt (point)))
10666 got-sigs (verilog-auto-sense-sigs moddecls nil))
10667 (when (not (or (verilog-signals-not-in pre-sigs got-sigs) ; Both are equal?
10668 (verilog-signals-not-in got-sigs pre-sigs)))
10669 (delete-region start-pt (point))
10670 (verilog-insert "/*AS*/")))))))
10672 (defun verilog-inject-inst ()
10673 "Inject AUTOINST into new code. See `verilog-inject-auto'."
10675 (goto-char (point-min))
10676 ;; It's hard to distinguish modules; we'll instead search for pins.
10677 (while (verilog-re-search-forward-quick "\\.\\s *[a-zA-Z0-9`_$]+\\s *(\\s *[a-zA-Z0-9`_$]+\\s *)" nil t)
10678 (verilog-backward-open-paren) ; Inst start
10680 ((= (preceding-char) ?\#) ; #(...) parameter section, not pin. Skip.
10682 (verilog-forward-close-paren)) ; Parameters done
10685 (let ((indent-pt (+ (current-column)))
10686 (end-pt (save-excursion (verilog-forward-close-paren) (point))))
10687 (cond ((verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-pt t)
10688 (goto-char end-pt)) ; Already there, continue search with next instance
10690 ;; Delete identical interconnect
10691 (let ((case-fold-search nil)) ; So we don't convert upper-to-lower, etc
10692 (while (verilog-re-search-forward-quick "\\.\\s *\\([a-zA-Z0-9`_$]+\\)*\\s *(\\s *\\1\\s *)\\s *" end-pt t)
10693 (delete-region (match-beginning 0) (match-end 0))
10694 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))) ; Keep it correct
10695 (while (or (looking-at "[ \t\n\f,]+")
10696 (looking-at "//[^\n]*"))
10697 (delete-region (match-beginning 0) (match-end 0))
10698 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))))))
10699 (verilog-forward-close-paren)
10701 ;; Not verilog-re-search, as we don't want to strip comments
10702 (while (re-search-backward "[ \t\n\f]+" (- (point) 1) t)
10703 (delete-region (match-beginning 0) (match-end 0)))
10704 (verilog-insert "\n")
10705 (verilog-insert-indent "/*AUTOINST*/")))))))))
10711 (defun verilog-diff-buffers-p (b1 b2 &optional whitespace regexp)
10712 "Return nil if buffers B1 and B2 have same contents.
10713 Else, return point in B1 that first mismatches.
10714 If optional WHITESPACE true, ignore whitespace.
10715 If optional REGEXP, ignore differences matching it."
10717 (let* ((case-fold-search nil) ; compare-buffer-substrings cares
10718 (p1 (with-current-buffer b1 (goto-char (point-min))))
10719 (p2 (with-current-buffer b2 (goto-char (point-min))))
10720 (maxp1 (with-current-buffer b1 (point-max)))
10721 (maxp2 (with-current-buffer b2 (point-max)))
10724 (while (not (and (eq p1 op1) (eq p2 op2)))
10725 ;; If both windows have whitespace optionally skip over it.
10727 ;; skip-syntax-* doesn't count \n
10728 (with-current-buffer b1
10730 (skip-chars-forward " \t\n\r\f\v")
10732 (with-current-buffer b2
10734 (skip-chars-forward " \t\n\r\f\v")
10735 (setq p2 (point))))
10737 (with-current-buffer b1
10739 (when (looking-at regexp)
10740 (setq p1 (match-end 0))))
10741 (with-current-buffer b2
10743 (when (looking-at regexp)
10744 (setq p2 (match-end 0)))))
10745 (setq size (min (- maxp1 p1) (- maxp2 p2)))
10746 (setq progress (compare-buffer-substrings b2 p2 (+ size p2)
10747 b1 p1 (+ size p1)))
10748 (setq progress (if (zerop progress) size (1- (abs progress))))
10749 (setq op1 p1 op2 p2
10751 p2 (+ p2 progress)))
10753 (if (and (eq p1 maxp1) (eq p2 maxp2))
10756 (defun verilog-diff-file-with-buffer (f1 b2 &optional whitespace show)
10757 "View the differences between file F1 and buffer B2.
10758 This requires the external program `diff-command' to be in your `exec-path',
10759 and uses `diff-switches' in which you may want to have \"-u\" flag.
10760 Ignores WHITESPACE if t, and writes output to stdout if SHOW."
10761 ;; Similar to `diff-buffer-with-file' but works on XEmacs, and doesn't
10762 ;; call `diff' as `diff' has different calling semantics on different
10763 ;; versions of Emacs.
10764 (if (not (file-exists-p f1))
10765 (message "Buffer `%s' has no associated file on disk" (buffer-name b2))
10766 (with-temp-buffer "*Verilog-Diff*"
10767 (let ((outbuf (current-buffer))
10768 (f2 (make-temp-file "vm-diff-auto-")))
10771 (with-current-buffer b2
10774 (write-region (point-min) (point-max) f2 nil 'nomessage)))
10775 (call-process diff-command nil outbuf t
10776 diff-switches ; User may want -u in diff-switches
10777 (if whitespace "-b" "")
10779 ;; Print out results. Alternatively we could have call-processed
10780 ;; ourself, but this way we can reuse diff switches
10782 (with-current-buffer outbuf (message "%s" (buffer-string))))))
10784 (when (file-exists-p f2)
10785 (delete-file f2))))))
10787 (defun verilog-diff-report (b1 b2 diffpt)
10788 "Report differences detected with `verilog-diff-auto'.
10789 Differences are between buffers B1 and B2, starting at point
10790 DIFFPT. This function is called via `verilog-diff-function'."
10791 (let ((name1 (with-current-buffer b1 (buffer-file-name))))
10792 (verilog-warn "%s:%d: Difference in AUTO expansion found"
10793 name1 (with-current-buffer b1
10794 (count-lines (point-min) diffpt)))
10795 (cond (noninteractive
10796 (verilog-diff-file-with-buffer name1 b2 t t))
10798 (ediff-buffers b1 b2)))))
10800 (defun verilog-diff-auto ()
10801 "Expand AUTOs in a temporary buffer and indicate any change.
10802 Whitespace is ignored when detecting differences, but once a
10803 difference is detected, whitespace differences may be shown.
10805 To call this from the command line, see \\[verilog-batch-diff-auto].
10807 The action on differences is selected with
10808 `verilog-diff-function'. The default is `verilog-diff-report'
10809 which will report an error and run `ediff' in interactive mode,
10810 or `diff' in batch mode."
10812 (let ((b1 (current-buffer)) b2 diffpt
10813 (name1 (buffer-file-name))
10814 (newname "*Verilog-Diff*"))
10816 (when (get-buffer newname)
10817 (kill-buffer newname))
10818 (setq b2 (let (buffer-file-name) ; Else clone is upset
10819 (clone-buffer newname)))
10820 (with-current-buffer b2
10821 ;; auto requires the filename, but can't have same filename in two
10822 ;; buffers; so override both b1 and b2's names
10823 (let ((buffer-file-name name1))
10826 (with-current-buffer b1 (setq buffer-file-name nil))
10828 (when (not verilog-auto-star-save)
10829 (verilog-delete-auto-star-implicit)))
10830 ;; Restore name if unwind
10831 (with-current-buffer b1 (setq buffer-file-name name1)))))
10833 (setq diffpt (verilog-diff-buffers-p b1 b2 t verilog-diff-ignore-regexp))
10834 (cond ((not diffpt)
10835 (unless noninteractive (message "AUTO expansion identical"))
10836 (kill-buffer newname)) ; Nice to cleanup after oneself
10838 (funcall verilog-diff-function b1 b2 diffpt)))
10839 ;; Return result of compare
10846 (defun verilog-auto-save-check ()
10847 "On saving see if we need auto update."
10848 (cond ((not verilog-auto-save-policy)) ; disabled
10849 ((not (save-excursion
10851 (let ((case-fold-search nil))
10852 (goto-char (point-min))
10853 (re-search-forward "AUTO" nil t))))))
10854 ((eq verilog-auto-save-policy 'force)
10856 ((not (buffer-modified-p)))
10857 ((eq verilog-auto-update-tick (buffer-chars-modified-tick))) ; up-to-date
10858 ((eq verilog-auto-save-policy 'detect)
10861 (when (yes-or-no-p "AUTO statements not recomputed, do it now? ")
10863 ;; Don't ask again if didn't update
10864 (set (make-local-variable 'verilog-auto-update-tick) (buffer-chars-modified-tick))))
10865 (when (not verilog-auto-star-save)
10866 (verilog-delete-auto-star-implicit))
10867 nil) ; Always return nil -- we don't write the file ourselves
10869 (defun verilog-auto-read-locals ()
10870 "Return file local variable segment at bottom of file."
10872 (goto-char (point-max))
10873 (if (re-search-backward "Local Variables:" nil t)
10874 (buffer-substring-no-properties (point) (point-max))
10877 (defun verilog-auto-reeval-locals (&optional force)
10878 "Read file local variable segment at bottom of file if it has changed.
10879 If FORCE, always reread it."
10880 (let ((curlocal (verilog-auto-read-locals)))
10881 (when (or force (not (equal verilog-auto-last-file-locals curlocal)))
10882 (set (make-local-variable 'verilog-auto-last-file-locals) curlocal)
10883 ;; Note this may cause this function to be recursively invoked,
10884 ;; because hack-local-variables may call (verilog-mode)
10885 ;; The above when statement will prevent it from recursing forever.
10886 (hack-local-variables)
10892 (defun verilog-auto-arg-ports (sigs message indent-pt)
10893 "Print a list of ports for AUTOARG.
10894 Takes SIGS list, adds MESSAGE to front and inserts each at INDENT-PT."
10896 (when verilog-auto-arg-sort
10897 (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
10899 (indent-to indent-pt)
10903 (indent-to indent-pt)
10905 (cond ((equal verilog-auto-arg-format 'single)
10907 (indent-to indent-pt)
10909 ;; verilog-auto-arg-format 'packed
10910 ((> (+ 2 (current-column) (length (verilog-sig-name (car sigs)))) fill-column)
10912 (indent-to indent-pt)
10917 (insert (verilog-sig-name (car sigs)) ",")
10918 (setq sigs (cdr sigs))))))
10920 (defun verilog-auto-arg ()
10921 "Expand AUTOARG statements.
10922 Replace the argument declarations at the beginning of the
10923 module with ones automatically derived from input and output
10924 statements. This can be dangerous if the module is instantiated
10925 using position-based connections, so use only name-based when
10926 instantiating the resulting module. Long lines are split based
10927 on the `fill-column', see \\[set-fill-column].
10930 Concatenation and outputting partial buses is not supported.
10932 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
10936 module ExampArg (/*AUTOARG*/);
10941 Typing \\[verilog-auto] will make this into:
10943 module ExampArg (/*AUTOARG*/
10953 The argument declarations may be printed in declaration order to
10954 best suit order based instantiations, or alphabetically, based on
10955 the `verilog-auto-arg-sort' variable.
10957 Formatting is controlled with `verilog-auto-arg-format' variable.
10959 Any ports declared between the ( and /*AUTOARG*/ are presumed to be
10960 predeclared and are not redeclared by AUTOARG. AUTOARG will make a
10961 conservative guess on adding a comma for the first signal, if you have
10962 any ifdefs or complicated expressions before the AUTOARG you will need
10963 to choose the comma yourself.
10965 Avoid declaring ports manually, as it makes code harder to maintain."
10967 (let* ((modi (verilog-modi-current))
10968 (moddecls (verilog-modi-get-decls modi))
10969 (skip-pins (aref (verilog-read-arg-pins) 0)))
10970 (verilog-repair-open-comma)
10971 (verilog-auto-arg-ports (verilog-signals-not-in
10972 (verilog-decls-get-outputs moddecls)
10975 verilog-indent-level-declaration)
10976 (verilog-auto-arg-ports (verilog-signals-not-in
10977 (verilog-decls-get-inouts moddecls)
10980 verilog-indent-level-declaration)
10981 (verilog-auto-arg-ports (verilog-signals-not-in
10982 (verilog-decls-get-inputs moddecls)
10985 verilog-indent-level-declaration)
10986 (verilog-repair-close-comma)
10987 (unless (eq (char-before) ?/ )
10989 (indent-to verilog-indent-level-declaration))))
10991 (defun verilog-auto-assign-modport ()
10992 "Expand AUTOASSIGNMODPORT statements, as part of \\[verilog-auto].
10993 Take input/output/inout statements from the specified interface
10994 and modport and use to build assignments into the modport, for
10995 making verification modules that connect to UVM interfaces.
10997 The first parameter is the name of an interface.
10999 The second parameter is a regexp of modports to read from in
11002 The third parameter is the instance name to use to dot reference into.
11004 The optional fourth parameter is a regular expression, and only
11005 signals matching the regular expression will be included.
11009 Interface names must be resolvable to filenames. See `verilog-auto-inst'.
11011 Inouts are not supported, as assignments must be unidirectional.
11013 If a signal is part of the interface header and in both a
11014 modport and the interface itself, it will not be listed. (As
11015 this would result in a syntax error when the connections are
11018 See the example in `verilog-auto-inout-modport'."
11020 (let* ((params (verilog-read-auto-params 3 4))
11021 (submod (nth 0 params))
11022 (modport-re (nth 1 params))
11023 (inst-name (nth 2 params))
11024 (regexp (nth 3 params))
11025 direction-re submodi) ; direction argument not supported until requested
11026 ;; Lookup position, etc of co-module
11027 ;; Note this may raise an error
11028 (when (setq submodi (verilog-modi-lookup submod t))
11029 (let* ((indent-pt (current-indentation))
11030 (submoddecls (verilog-modi-get-decls submodi))
11031 (submodportdecls (verilog-modi-modport-lookup submodi modport-re))
11032 (sig-list-i (verilog-signals-in ; Decls doesn't have data types, must resolve
11033 (verilog-decls-get-vars submoddecls)
11034 (verilog-signals-not-in
11035 (verilog-decls-get-inputs submodportdecls)
11036 (verilog-decls-get-ports submoddecls))))
11037 (sig-list-o (verilog-signals-in ; Decls doesn't have data types, must resolve
11038 (verilog-decls-get-vars submoddecls)
11039 (verilog-signals-not-in
11040 (verilog-decls-get-outputs submodportdecls)
11041 (verilog-decls-get-ports submoddecls)))))
11043 (setq sig-list-i (verilog-signals-edit-wire-reg
11044 (verilog-signals-matching-dir-re
11045 (verilog-signals-matching-regexp sig-list-i regexp)
11046 "input" direction-re))
11047 sig-list-o (verilog-signals-edit-wire-reg
11048 (verilog-signals-matching-dir-re
11049 (verilog-signals-matching-regexp sig-list-o regexp)
11050 "output" direction-re)))
11051 (setq sig-list-i (sort (copy-alist sig-list-i) `verilog-signals-sort-compare))
11052 (setq sig-list-o (sort (copy-alist sig-list-o) `verilog-signals-sort-compare))
11053 (when (or sig-list-i sig-list-o)
11054 (verilog-insert-indent "// Beginning of automatic assignments from modport\n")
11055 ;; Don't sort them so an upper AUTOINST will match the main module
11056 (let ((sigs sig-list-o))
11058 (verilog-insert-indent "assign " (verilog-sig-name (car sigs))
11060 "." (verilog-sig-name (car sigs)) ";\n")
11061 (setq sigs (cdr sigs))))
11062 (let ((sigs sig-list-i))
11064 (verilog-insert-indent "assign " inst-name
11065 "." (verilog-sig-name (car sigs))
11066 " = " (verilog-sig-name (car sigs)) ";\n")
11067 (setq sigs (cdr sigs))))
11068 (verilog-insert-indent "// End of automatics\n")))))))
11070 (defun verilog-auto-inst-port-map (_port-st)
11073 (defvar vl-cell-type nil "See `verilog-auto-inst'.") ; Prevent compile warning
11074 (defvar vl-cell-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
11075 (defvar vl-modport nil "See `verilog-auto-inst'.") ; Prevent compile warning
11076 (defvar vl-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
11077 (defvar vl-width nil "See `verilog-auto-inst'.") ; Prevent compile warning
11078 (defvar vl-dir nil "See `verilog-auto-inst'.") ; Prevent compile warning
11079 (defvar vl-bits nil "See `verilog-auto-inst'.") ; Prevent compile warning
11080 (defvar vl-mbits nil "See `verilog-auto-inst'.") ; Prevent compile warning
11082 (defun verilog-auto-inst-port (port-st indent-pt moddecls tpl-list tpl-num for-star par-values)
11083 "Print out an instantiation connection for this PORT-ST.
11084 Insert to INDENT-PT, use template TPL-LIST.
11085 @ are instantiation numbers, replaced with TPL-NUM.
11086 @\"(expression @)\" are evaluated, with @ as a variable.
11087 If FOR-STAR add comment it is a .* expansion.
11088 If PAR-VALUES replace final strings with these parameter values."
11089 (let* ((port (verilog-sig-name port-st))
11090 (tpl-ass (or (assoc port (car tpl-list))
11091 (verilog-auto-inst-port-map port-st)))
11092 ;; vl-* are documented for user use
11093 (vl-name (verilog-sig-name port-st))
11094 (vl-width (verilog-sig-width port-st))
11095 (vl-modport (verilog-sig-modport port-st))
11096 (vl-memory (verilog-sig-memory port-st))
11097 (vl-mbits (if (verilog-sig-multidim port-st)
11098 (verilog-sig-multidim-string port-st) ""))
11099 (vl-bits (if (or verilog-auto-inst-vector
11100 (not (assoc port (verilog-decls-get-signals moddecls)))
11101 (not (equal (verilog-sig-bits port-st)
11103 (assoc port (verilog-decls-get-signals moddecls))))))
11104 (or (verilog-sig-bits port-st) "")
11106 (case-fold-search nil)
11107 (check-values par-values)
11109 ;; Replace parameters in bit-width
11110 (when (and check-values
11111 (not (equal vl-bits "")))
11112 (while check-values
11113 (setq vl-bits (verilog-string-replace-matches
11114 (concat "\\<" (nth 0 (car check-values)) "\\>")
11115 (concat "(" (nth 1 (car check-values)) ")")
11117 vl-mbits (verilog-string-replace-matches
11118 (concat "\\<" (nth 0 (car check-values)) "\\>")
11119 (concat "(" (nth 1 (car check-values)) ")")
11121 vl-memory (when vl-memory
11122 (verilog-string-replace-matches
11123 (concat "\\<" (nth 0 (car check-values)) "\\>")
11124 (concat "(" (nth 1 (car check-values)) ")")
11126 check-values (cdr check-values)))
11127 (setq vl-bits (verilog-simplify-range-expression vl-bits)
11128 vl-mbits (verilog-simplify-range-expression vl-mbits)
11129 vl-memory (when vl-memory (verilog-simplify-range-expression vl-memory))
11130 vl-width (verilog-make-width-expression vl-bits))) ; Not in the loop for speed
11131 ;; Default net value if not found
11132 (setq dflt-bits (if (or (and (verilog-sig-bits port-st)
11133 (verilog-sig-multidim port-st))
11134 (verilog-sig-memory port-st))
11135 (concat "/*" vl-mbits vl-bits
11136 ;; .[ used to separate packed from unpacked
11137 (if vl-memory "." "")
11138 (if vl-memory vl-memory "")
11141 tpl-net (concat port
11142 (if (and vl-modport
11143 ;; .modport cannot be added if attachment is
11144 ;; already declared as modport, VCS croaks
11145 (let ((sig (assoc port (verilog-decls-get-interfaces moddecls))))
11146 (not (and sig (verilog-sig-modport sig)))))
11147 (concat "." vl-modport) "")
11150 (cond (tpl-ass ; Template of exact port name
11151 (setq tpl-net (nth 1 tpl-ass)))
11152 ((nth 1 tpl-list) ; Wildcards in template, search them
11153 (let ((wildcards (nth 1 tpl-list)))
11155 (when (string-match (nth 0 (car wildcards)) port)
11156 (setq tpl-ass (car wildcards) ; so allow @ parsing
11157 tpl-net (replace-match (nth 1 (car wildcards))
11159 (setq wildcards (cdr wildcards))))))
11160 ;; Parse Templated variable
11162 ;; Evaluate @"(lispcode)"
11163 (when (string-match "@\".*[^\\]\"" tpl-net)
11164 (while (string-match "@\"\\(\\([^\\\"]*\\(\\\\.\\)*\\)*\\)\"" tpl-net)
11167 (substring tpl-net 0 (match-beginning 0))
11169 (let* ((expr (match-string 1 tpl-net))
11172 (setq expr (verilog-string-replace-matches "\\\\\"" "\"" nil nil expr))
11173 (setq expr (verilog-string-replace-matches "@" tpl-num nil nil expr))
11174 (prin1 (eval (car (read-from-string expr)))
11175 (lambda (_ch) ())))))
11176 (if (numberp value) (setq value (number-to-string value)))
11178 (substring tpl-net (match-end 0))))))
11179 ;; Replace @ and [] magic variables in final output
11180 (setq tpl-net (verilog-string-replace-matches "@" tpl-num nil nil tpl-net))
11181 (setq tpl-net (verilog-string-replace-matches "\\[\\]\\[\\]" dflt-bits nil nil tpl-net))
11182 (setq tpl-net (verilog-string-replace-matches "\\[\\]" vl-bits nil nil tpl-net)))
11184 (indent-to indent-pt)
11186 (unless (and verilog-auto-inst-dot-name
11187 (equal port tpl-net))
11188 (indent-to verilog-auto-inst-column)
11189 (insert "(" tpl-net ")"))
11192 (verilog-read-auto-template-hit tpl-ass)
11193 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
11194 verilog-auto-inst-column))
11195 ;; verilog-insert requires the complete comment in one call - including the newline
11196 (cond ((equal verilog-auto-inst-template-numbers `lhs)
11197 (verilog-insert " // Templated"
11198 " LHS: " (nth 0 tpl-ass)
11200 (verilog-auto-inst-template-numbers
11201 (verilog-insert " // Templated"
11202 " T" (int-to-string (nth 2 tpl-ass))
11203 " L" (int-to-string (nth 3 tpl-ass))
11206 (verilog-insert " // Templated\n"))))
11208 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
11209 verilog-auto-inst-column))
11210 (verilog-insert " // Implicit .*\n"))
11213 ;;(verilog-auto-inst-port (list "foo" "[5:0]") 10 (list (list "foo" "a@\"(% (+ @ 1) 4)\"a")) "3")
11214 ;;(x "incom[@\"(+ (* 8 @) 7)\":@\"(* 8 @)\"]")
11215 ;;(x ".out (outgo[@\"(concat (+ (* 8 @) 7) \\\":\\\" ( * 8 @))\"]));")
11217 (defun verilog-auto-inst-port-list (sig-list indent-pt moddecls tpl-list tpl-num for-star par-values)
11218 "For `verilog-auto-inst' print a list of ports using `verilog-auto-inst-port'."
11219 (when verilog-auto-inst-sort
11220 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare)))
11221 (mapc (lambda (port)
11222 (verilog-auto-inst-port port indent-pt moddecls
11223 tpl-list tpl-num for-star par-values))
11226 (defun verilog-auto-inst-first ()
11227 "Insert , etc before first ever port in this instant, as part of \\[verilog-auto-inst]."
11228 ;; Do we need a trailing comma?
11229 ;; There maybe an ifdef or something similar before us. What a mess. Thus
11230 ;; to avoid trouble we only insert on preceding ) or *.
11231 ;; Insert first port on new line
11232 (insert "\n") ; Must insert before search, so point will move forward if insert comma
11234 (verilog-re-search-backward-quick "[^ \t\n\f]" nil nil)
11235 (when (looking-at ")\\|\\*") ; Generally don't insert, unless we are fairly sure
11239 (defun verilog-auto-star ()
11240 "Expand SystemVerilog .* pins, as part of \\[verilog-auto].
11242 If `verilog-auto-star-expand' is set, .* pins are treated if they were
11243 AUTOINST statements, otherwise they are ignored. For safety, Verilog mode
11244 will also ignore any .* that are not last in your pin list (this prevents
11245 it from deleting pins following the .* when it expands the AUTOINST.)
11247 On writing your file, unless `verilog-auto-star-save' is set, any
11248 non-templated expanded pins will be removed. You may do this at any time
11249 with \\[verilog-delete-auto-star-implicit].
11251 If you are converting a module to use .* for the first time, you may wish
11252 to use \\[verilog-inject-auto] and then replace the created AUTOINST with .*.
11254 See `verilog-auto-inst' for examples, templates, and more information."
11255 (when (verilog-auto-star-safe)
11256 (verilog-auto-inst)))
11258 (defun verilog-auto-inst ()
11259 "Expand AUTOINST statements, as part of \\[verilog-auto].
11260 Replace the pin connections to an instantiation or interface
11261 declaration with ones automatically derived from the module or
11262 interface header of the instantiated item.
11264 If `verilog-auto-star-expand' is set, also expand SystemVerilog .* ports,
11265 and delete them before saving unless `verilog-auto-star-save' is set.
11266 See `verilog-auto-star' for more information.
11268 The pins are printed in declaration order or alphabetically,
11269 based on the `verilog-auto-inst-sort' variable.
11272 Module names must be resolvable to filenames by adding a
11273 `verilog-library-extensions', and being found in the same directory, or
11274 by changing the variable `verilog-library-flags' or
11275 `verilog-library-directories'. Macros `modname are translated through the
11276 vh-{name} Emacs variable, if that is not found, it just ignores the \\=`.
11278 In templates you must have one signal per line, ending in a ), or ));,
11279 and have proper () nesting, including a final ); to end the template.
11281 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
11283 SystemVerilog multidimensional input/output has only experimental support.
11285 SystemVerilog .name syntax is used if `verilog-auto-inst-dot-name' is set.
11287 Parameters referenced by the instantiation will remain symbolic, unless
11288 `verilog-auto-inst-param-value' is set.
11290 Gate primitives (and/or) may have AUTOINST for the purpose of
11291 AUTOWIRE declarations, etc. Gates are the only case when
11292 position based connections are passed.
11294 The array part of arrayed instances are ignored; this may
11295 result in undesirable default AUTOINST connections; use a
11298 For example, first take the submodule InstModule.v:
11300 module InstModule (o,i);
11303 wire [31:0] o = {32{i}};
11306 This is then used in an upper level module:
11308 module ExampInst (o,i);
11311 InstModule instName
11315 Typing \\[verilog-auto] will make this into:
11317 module ExampInst (o,i);
11320 InstModule instName
11328 Where the list of inputs and outputs came from the inst module.
11332 Unless you are instantiating a module multiple times, or the module is
11333 something trivial like an adder, DO NOT CHANGE SIGNAL NAMES ACROSS HIERARCHY.
11334 It just makes for unmaintainable code. To sanitize signal names, try
11335 vrename from URL `http://www.veripool.org'.
11337 When you need to violate this suggestion there are two ways to list
11338 exceptions, placing them before the AUTOINST, or using templates.
11340 Any ports defined before the /*AUTOINST*/ are not included in the list of
11341 automatics. This is similar to making a template as described below, but
11342 is restricted to simple connections just like you normally make. Also note
11343 that any signals before the AUTOINST will only be picked up by AUTOWIRE if
11344 you have the appropriate // Input or // Output comment, and exactly the
11345 same line formatting as AUTOINST itself uses.
11347 InstModule instName
11349 .i (my_i_dont_mess_with_it),
11357 For multiple instantiations based upon a single template, create a
11358 commented out template:
11360 /* InstModule AUTO_TEMPLATE (
11365 Templates go ABOVE the instantiation(s). When an instantiation is
11366 expanded `verilog-mode' simply searches up for the closest template.
11367 Thus you can have multiple templates for the same module, just alternate
11368 between the template for an instantiation and the instantiation itself.
11369 (For backward compatibility if no template is found above, it
11370 will also look below, but do not use this behavior in new designs.)
11372 The module name must be the same as the name of the module in the
11373 instantiation name, and the code \"AUTO_TEMPLATE\" must be in these exact
11374 words and capitalized. Only signals that must be different for each
11375 instantiation need to be listed.
11377 Inside a template, a [] in a connection name (with nothing else
11378 inside the brackets) will be replaced by the same bus subscript
11379 as it is being connected to, or the [] will be removed if it is
11380 a single bit signal.
11382 Inside a template, a [][] in a connection name will behave
11383 similarly to a [] for scalar or single-dimensional connection;
11384 for a multidimensional connection it will print a comment
11385 similar to that printed when a template is not used. Generally
11386 it is a good idea to do this for all connections in a template,
11387 as then they will work for any width signal, and with AUTOWIRE.
11388 See PTL_BUS becoming PTL_BUSNEW below.
11390 Inside a template, a [] in a connection name (with nothing else inside
11391 the brackets) will be replaced by the same bus subscript as it is being
11392 connected to, or the [] will be removed if it is a single bit signal.
11393 Generally it is a good idea to do this for all connections in a template,
11394 as then they will work for any width signal, and with AUTOWIRE. See
11395 PTL_BUS becoming PTL_BUSNEW below.
11397 If you have a complicated template, set `verilog-auto-inst-template-numbers'
11398 to see which regexps are matching. Don't leave that mode set after
11399 debugging is completed though, it will result in lots of extra differences
11400 and merge conflicts.
11402 Setting `verilog-auto-template-warn-unused' will report errors
11403 if any template lines are unused.
11407 /* InstModule AUTO_TEMPLATE (
11408 .ptl_bus (ptl_busnew[]),
11411 InstModule ms2m (/*AUTOINST*/);
11413 Typing \\[verilog-auto] will make this into:
11415 InstModule ms2m (/*AUTOINST*/
11417 .NotInTemplate (NotInTemplate),
11418 .ptl_bus (ptl_busnew[3:0]), // Templated
11422 Multiple Module Templates:
11424 The same template lines can be applied to multiple modules with
11425 the syntax as follows:
11427 /* InstModuleA AUTO_TEMPLATE
11428 InstModuleB AUTO_TEMPLATE
11429 InstModuleC AUTO_TEMPLATE
11430 InstModuleD AUTO_TEMPLATE (
11431 .ptl_bus (ptl_busnew[]),
11435 Note there is only one AUTO_TEMPLATE opening parenthesis.
11439 It is common to instantiate a cell multiple times, so templates make it
11440 trivial to substitute part of the cell name into the connection name.
11442 /* InstName AUTO_TEMPLATE <optional \"REGEXP\"> (
11444 .sig2 (sigy[@\"(% (+ 1 @) 4)\"]),
11448 If no regular expression is provided immediately after the AUTO_TEMPLATE
11449 keyword, then the @ character in any connection names will be replaced
11450 with the instantiation number; the first digits found in the cell's
11451 instantiation name.
11453 If a regular expression is provided, the @ character will be replaced
11454 with the first () grouping that matches against the cell name. Using a
11455 regexp of `\\([0-9]+\\)' provides identical values for @ as when no
11456 regexp is provided. If you use multiple layers of parenthesis,
11457 `test\\([^0-9]+\\)_\\([0-9]+\\)' would replace @ with non-number
11458 characters after test and before _, whereas
11459 `\\(test\\([a-z]+\\)_\\([0-9]+\\)\\)' would replace @ with the entire
11464 /* InstModule AUTO_TEMPLATE (
11465 .ptl_mapvalidx (ptl_mapvalid[@]),
11466 .ptl_mapvalidp1x (ptl_mapvalid[@\"(% (+ 1 @) 4)\"]),
11469 InstModule ms2m (/*AUTOINST*/);
11471 Typing \\[verilog-auto] will make this into:
11473 InstModule ms2m (/*AUTOINST*/
11475 .ptl_mapvalidx (ptl_mapvalid[2]),
11476 .ptl_mapvalidp1x (ptl_mapvalid[3]));
11478 Note the @ character was replaced with the 2 from \"ms2m\".
11480 Alternatively, using a regular expression for @:
11482 /* InstModule AUTO_TEMPLATE \"_\\([a-z]+\\)\" (
11483 .ptl_mapvalidx (@_ptl_mapvalid),
11484 .ptl_mapvalidp1x (ptl_mapvalid_@),
11487 InstModule ms2_FOO (/*AUTOINST*/);
11488 InstModule ms2_BAR (/*AUTOINST*/);
11490 Typing \\[verilog-auto] will make this into:
11492 InstModule ms2_FOO (/*AUTOINST*/
11494 .ptl_mapvalidx (FOO_ptl_mapvalid),
11495 .ptl_mapvalidp1x (ptl_mapvalid_FOO));
11496 InstModule ms2_BAR (/*AUTOINST*/
11498 .ptl_mapvalidx (BAR_ptl_mapvalid),
11499 .ptl_mapvalidp1x (ptl_mapvalid_BAR));
11504 A template entry of the form
11506 .pci_req\\([0-9]+\\)_l (pci_req_jtag_[\\1]),
11508 will apply an Emacs style regular expression search for any port beginning
11509 in pci_req followed by numbers and ending in _l and connecting that to
11510 the pci_req_jtag_[] net, with the bus subscript coming from what matches
11511 inside the first set of \\( \\). Thus pci_req2_l becomes pci_req_jtag_[2].
11513 Since \\([0-9]+\\) is so common and ugly to read, a @ in the port name
11514 does the same thing. (Note a @ in the connection/replacement text is
11515 completely different -- still use \\1 there!) Thus this is the same as
11516 the above template:
11518 .pci_req@_l (pci_req_jtag_[\\1]),
11520 Here's another example to remove the _l, useful when naming conventions
11521 specify _ alone to mean active low. Note the use of [] to keep the bus
11524 .\\(.*\\)_l (\\1_[]),
11528 First any regular expression template is expanded.
11530 If the syntax @\"( ... )\" is found in a connection, the expression in
11531 quotes will be evaluated as a Lisp expression, with @ replaced by the
11532 instantiation number. The MAPVALIDP1X example above would put @+1 modulo
11533 4 into the brackets. Quote all double-quotes inside the expression with
11534 a leading backslash (\\\"...\\\"); or if the Lisp template is also a
11535 regexp template backslash the backslash quote (\\\\\"...\\\\\").
11537 There are special variables defined that are useful in these
11540 vl-name Name portion of the input/output port.
11541 vl-bits Bus bits portion of the input/output port (`[2:0]').
11542 vl-mbits Multidimensional array bits for port (`[2:0][3:0]').
11543 vl-width Width of the input/output port (`3' for [2:0]).
11544 May be a (...) expression if bits isn't a constant.
11545 vl-dir Direction of the pin input/output/inout/interface.
11546 vl-modport The modport, if an interface with a modport.
11547 vl-cell-type Module name/type of the cell (`InstModule').
11548 vl-cell-name Instance name of the cell (`instName').
11550 Normal Lisp variables may be used in expressions. See
11551 `verilog-read-defines' which can set vh-{definename} variables for use
11552 here. Also, any comments of the form:
11554 /*AUTO_LISP(setq foo 1)*/
11556 will evaluate any Lisp expression inside the parenthesis between the
11557 beginning of the buffer and the point of the AUTOINST. This allows
11558 functions to be defined or variables to be changed between instantiations.
11559 (See also `verilog-auto-insert-lisp' if you want the output from your
11560 lisp function to be inserted.)
11562 Note that when using lisp expressions errors may occur when @ is not a
11563 number; you may need to use the standard Emacs Lisp functions
11564 `number-to-string' and `string-to-number'.
11566 After the evaluation is completed, @ substitution and [] substitution
11569 For more information see the \\[verilog-faq] and forums at URL
11570 `http://www.veripool.org'."
11573 (let* ((pt (point))
11574 (for-star (save-excursion (backward-char 2) (looking-at "\\.\\*")))
11575 (indent-pt (save-excursion (verilog-backward-open-paren)
11576 (1+ (current-column))))
11577 (verilog-auto-inst-column (max verilog-auto-inst-column
11578 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
11579 (modi (verilog-modi-current))
11580 (moddecls (verilog-modi-get-decls modi))
11581 submod submodi submoddecls
11582 inst skip-pins tpl-list tpl-num did-first par-values)
11584 ;; Find module name that is instantiated
11585 (setq submod (verilog-read-inst-module)
11586 inst (verilog-read-inst-name)
11587 vl-cell-type submod
11589 skip-pins (aref (verilog-read-inst-pins) 0))
11591 ;; Parse any AUTO_LISP() before here
11592 (verilog-read-auto-lisp (point-min) pt)
11594 ;; Read parameters (after AUTO_LISP)
11595 (setq par-values (and verilog-auto-inst-param-value
11596 (verilog-read-inst-param-value)))
11598 ;; Lookup position, etc of submodule
11599 ;; Note this may raise an error
11600 (when (and (not (member submod verilog-gate-keywords))
11601 (setq submodi (verilog-modi-lookup submod t)))
11602 (setq submoddecls (verilog-modi-get-decls submodi))
11603 ;; If there's a number in the instantiation, it may be an argument to the
11604 ;; automatic variable instantiation program.
11605 (let* ((tpl-info (verilog-read-auto-template submod))
11606 (tpl-regexp (aref tpl-info 0)))
11607 (setq tpl-num (if (verilog-string-match-fold tpl-regexp inst)
11608 (match-string 1 inst)
11610 tpl-list (aref tpl-info 1)))
11611 ;; Find submodule's signals and dump
11612 (let ((sig-list (and (equal (verilog-modi-get-type submodi) "interface")
11613 (verilog-signals-not-in
11614 (verilog-decls-get-vars submoddecls)
11616 (vl-dir "interfaced"))
11617 (when (and sig-list
11618 verilog-auto-inst-interfaced-ports)
11619 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11620 ;; Note these are searched for in verilog-read-sub-decls.
11621 (verilog-insert-indent "// Interfaced\n")
11622 (verilog-auto-inst-port-list sig-list indent-pt moddecls
11623 tpl-list tpl-num for-star par-values)))
11624 (let ((sig-list (verilog-signals-not-in
11625 (verilog-decls-get-interfaces submoddecls)
11627 (vl-dir "interface"))
11629 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11630 ;; Note these are searched for in verilog-read-sub-decls.
11631 (verilog-insert-indent "// Interfaces\n")
11632 (verilog-auto-inst-port-list sig-list indent-pt moddecls
11633 tpl-list tpl-num for-star par-values)))
11634 (let ((sig-list (verilog-signals-not-in
11635 (verilog-decls-get-outputs submoddecls)
11639 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11640 (verilog-insert-indent "// Outputs\n")
11641 (verilog-auto-inst-port-list sig-list indent-pt moddecls
11642 tpl-list tpl-num for-star par-values)))
11643 (let ((sig-list (verilog-signals-not-in
11644 (verilog-decls-get-inouts submoddecls)
11648 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11649 (verilog-insert-indent "// Inouts\n")
11650 (verilog-auto-inst-port-list sig-list indent-pt moddecls
11651 tpl-list tpl-num for-star par-values)))
11652 (let ((sig-list (verilog-signals-not-in
11653 (verilog-decls-get-inputs submoddecls)
11657 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11658 (verilog-insert-indent "// Inputs\n")
11659 (verilog-auto-inst-port-list sig-list indent-pt moddecls
11660 tpl-list tpl-num for-star par-values)))
11664 (re-search-backward "," pt t)
11667 (search-forward "\n") ; Added by inst-port
11669 (if (search-forward ")" nil t) ; From user, moved up a line
11671 (if (search-forward ";" nil t) ; Don't error if user had syntax error and forgot it
11672 (delete-char -1)))))))))
11674 (defun verilog-auto-inst-param ()
11675 "Expand AUTOINSTPARAM statements, as part of \\[verilog-auto].
11676 Replace the parameter connections to an instantiation with ones
11677 automatically derived from the module header of the instantiated netlist.
11679 See \\[verilog-auto-inst] for limitations, and templates to customize the
11682 For example, first take the submodule InstModule.v:
11684 module InstModule (o,i);
11688 This is then used in an upper level module:
11690 module ExampInst (o,i);
11692 InstModule #(/*AUTOINSTPARAM*/)
11693 instName (/*AUTOINST*/);
11696 Typing \\[verilog-auto] will make this into:
11698 module ExampInst (o,i);
11701 InstModule #(/*AUTOINSTPARAM*/
11704 instName (/*AUTOINST*/);
11707 Where the list of parameter connections come from the inst module.
11711 You can customize the parameter connections using AUTO_TEMPLATEs,
11712 just as you would with \\[verilog-auto-inst]."
11715 (let* ((pt (point))
11716 (indent-pt (save-excursion (verilog-backward-open-paren)
11717 (1+ (current-column))))
11718 (verilog-auto-inst-column (max verilog-auto-inst-column
11719 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
11720 (modi (verilog-modi-current))
11721 (moddecls (verilog-modi-get-decls modi))
11722 submod submodi submoddecls
11723 inst skip-pins tpl-list tpl-num did-first)
11724 ;; Find module name that is instantiated
11725 (setq submod (save-excursion
11726 ;; Get to the point where AUTOINST normally is to read the module
11727 (verilog-re-search-forward-quick "[(;]" nil nil)
11728 (verilog-read-inst-module))
11729 inst (save-excursion
11730 ;; Get to the point where AUTOINST normally is to read the module
11731 (verilog-re-search-forward-quick "[(;]" nil nil)
11732 (verilog-read-inst-name))
11733 vl-cell-type submod
11735 skip-pins (aref (verilog-read-inst-pins) 0))
11737 ;; Parse any AUTO_LISP() before here
11738 (verilog-read-auto-lisp (point-min) pt)
11740 ;; Lookup position, etc of submodule
11741 ;; Note this may raise an error
11742 (when (setq submodi (verilog-modi-lookup submod t))
11743 (setq submoddecls (verilog-modi-get-decls submodi))
11744 ;; If there's a number in the instantiation, it may be an argument to the
11745 ;; automatic variable instantiation program.
11746 (let* ((tpl-info (verilog-read-auto-template submod))
11747 (tpl-regexp (aref tpl-info 0)))
11748 (setq tpl-num (if (verilog-string-match-fold tpl-regexp inst)
11749 (match-string 1 inst)
11751 tpl-list (aref tpl-info 1)))
11752 ;; Find submodule's signals and dump
11753 (let ((sig-list (verilog-signals-not-in
11754 (verilog-decls-get-gparams submoddecls)
11756 (vl-dir "parameter"))
11758 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11759 ;; Note these are searched for in verilog-read-sub-decls.
11760 (verilog-insert-indent "// Parameters\n")
11761 (verilog-auto-inst-port-list sig-list indent-pt moddecls
11762 tpl-list tpl-num nil nil)))
11766 (re-search-backward "," pt t)
11769 (search-forward "\n") ; Added by inst-port
11771 (if (search-forward ")" nil t) ; From user, moved up a line
11772 (delete-char -1)))))))))
11774 (defun verilog-auto-reg ()
11775 "Expand AUTOREG statements, as part of \\[verilog-auto].
11776 Make reg statements for any output that isn't already declared,
11777 and isn't a wire output from a block. `verilog-auto-wire-type'
11778 may be used to change the datatype of the declarations.
11781 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
11783 This does NOT work on memories, declare those yourself.
11787 module ExampReg (o,i);
11794 Typing \\[verilog-auto] will make this into:
11796 module ExampReg (o,i);
11800 // Beginning of automatic regs (for this module's undeclared outputs)
11802 // End of automatics
11806 ;; Point must be at insertion point.
11807 (let* ((indent-pt (current-indentation))
11808 (modi (verilog-modi-current))
11809 (moddecls (verilog-modi-get-decls modi))
11810 (modsubdecls (verilog-modi-get-sub-decls modi))
11811 (sig-list (verilog-signals-not-in
11812 (verilog-decls-get-outputs moddecls)
11813 (append (verilog-signals-with ; ignore typed signals
11815 (verilog-decls-get-outputs moddecls))
11816 (verilog-decls-get-vars moddecls)
11817 (verilog-decls-get-assigns moddecls)
11818 (verilog-decls-get-consts moddecls)
11819 (verilog-decls-get-gparams moddecls)
11820 (verilog-subdecls-get-interfaced modsubdecls)
11821 (verilog-subdecls-get-outputs modsubdecls)
11822 (verilog-subdecls-get-inouts modsubdecls)))))
11824 (verilog-forward-or-insert-line)
11825 (verilog-insert-indent "// Beginning of automatic regs (for this module's undeclared outputs)\n")
11826 (verilog-insert-definition modi sig-list "reg" indent-pt nil)
11827 (verilog-insert-indent "// End of automatics\n")))))
11829 (defun verilog-auto-reg-input ()
11830 "Expand AUTOREGINPUT statements, as part of \\[verilog-auto].
11831 Make reg statements instantiation inputs that aren't already declared.
11832 This is useful for making a top level shell for testing the module that is
11833 to be instantiated.
11836 This ONLY detects inputs of AUTOINSTants (see `verilog-read-sub-decls').
11838 This does NOT work on memories, declare those yourself.
11840 An example (see `verilog-auto-inst' for what else is going on here):
11842 module ExampRegInput (o,i);
11846 InstModule instName
11850 Typing \\[verilog-auto] will make this into:
11852 module ExampRegInput (o,i);
11856 // Beginning of automatic reg inputs (for undeclared ...
11857 reg [31:0] iv; // From inst of inst.v
11858 // End of automatics
11859 InstModule instName
11867 ;; Point must be at insertion point.
11868 (let* ((indent-pt (current-indentation))
11869 (modi (verilog-modi-current))
11870 (moddecls (verilog-modi-get-decls modi))
11871 (modsubdecls (verilog-modi-get-sub-decls modi))
11872 (sig-list (verilog-signals-combine-bus
11873 (verilog-signals-not-in
11874 (append (verilog-subdecls-get-inputs modsubdecls)
11875 (verilog-subdecls-get-inouts modsubdecls))
11876 (append (verilog-decls-get-signals moddecls)
11877 (verilog-decls-get-assigns moddecls))))))
11879 (verilog-forward-or-insert-line)
11880 (verilog-insert-indent "// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)\n")
11881 (verilog-insert-definition modi sig-list "reg" indent-pt nil)
11882 (verilog-insert-indent "// End of automatics\n")))))
11884 (defun verilog-auto-logic-setup ()
11885 "Prepare variables due to AUTOLOGIC."
11886 (unless verilog-auto-wire-type
11887 (set (make-local-variable 'verilog-auto-wire-type)
11890 (defun verilog-auto-logic ()
11891 "Expand AUTOLOGIC statements, as part of \\[verilog-auto].
11892 Make wire statements using the SystemVerilog logic keyword.
11893 This is currently equivalent to:
11897 with the below at the bottom of the file
11899 // Local Variables:
11900 // verilog-auto-logic-type:\"logic\"
11903 In the future AUTOLOGIC may declare additional identifiers,
11904 while AUTOWIRE will not."
11906 (verilog-auto-logic-setup)
11907 (verilog-auto-wire)))
11909 (defun verilog-auto-wire ()
11910 "Expand AUTOWIRE statements, as part of \\[verilog-auto].
11911 Make wire statements for instantiations outputs that aren't
11912 already declared. `verilog-auto-wire-type' may be used to change
11913 the datatype of the declarations.
11916 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'),
11917 and all buses must have widths, such as those from AUTOINST, or using []
11920 This does NOT work on memories or SystemVerilog .name connections,
11921 declare those yourself.
11923 Verilog mode will add \"Couldn't Merge\" comments to signals it cannot
11924 determine how to bus together. This occurs when you have ports with
11925 non-numeric or non-sequential bus subscripts. If Verilog mode
11926 mis-guessed, you'll have to declare them yourself.
11928 An example (see `verilog-auto-inst' for what else is going on here):
11930 module ExampWire (o,i);
11934 InstModule instName
11938 Typing \\[verilog-auto] will make this into:
11940 module ExampWire (o,i);
11944 // Beginning of automatic wires
11945 wire [31:0] ov; // From inst of inst.v
11946 // End of automatics
11947 InstModule instName
11956 ;; Point must be at insertion point.
11957 (let* ((indent-pt (current-indentation))
11958 (modi (verilog-modi-current))
11959 (moddecls (verilog-modi-get-decls modi))
11960 (modsubdecls (verilog-modi-get-sub-decls modi))
11961 (sig-list (verilog-signals-combine-bus
11962 (verilog-signals-not-in
11963 (append (verilog-subdecls-get-outputs modsubdecls)
11964 (verilog-subdecls-get-inouts modsubdecls))
11965 (verilog-decls-get-signals moddecls)))))
11967 (verilog-forward-or-insert-line)
11968 (verilog-insert-indent "// Beginning of automatic wires (for undeclared instantiated-module outputs)\n")
11969 (verilog-insert-definition modi sig-list "wire" indent-pt nil)
11970 (verilog-insert-indent "// End of automatics\n")
11971 ;; We used to optionally call verilog-pretty-declarations and
11972 ;; verilog-pretty-expr here, but it's too slow on huge modules,
11973 ;; plus makes everyone's module change. Finally those call
11974 ;; syntax-ppss which is broken when change hooks are disabled.
11977 (defun verilog-auto-output ()
11978 "Expand AUTOOUTPUT statements, as part of \\[verilog-auto].
11979 Make output statements for any output signal from an /*AUTOINST*/ that
11980 isn't an input to another AUTOINST. This is useful for modules which
11981 only instantiate other modules.
11984 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
11986 If placed inside the parenthesis of a module declaration, it creates
11987 Verilog 2001 style, else uses Verilog 1995 style.
11989 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
11990 instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
11992 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
11994 Types are added to declarations if an AUTOLOGIC or
11995 `verilog-auto-wire-type' is set to logic.
11997 Signals matching `verilog-auto-output-ignore-regexp' are not included.
11999 An example (see `verilog-auto-inst' for what else is going on here):
12001 module ExampOutput (ov,i);
12004 InstModule instName
12008 Typing \\[verilog-auto] will make this into:
12010 module ExampOutput (ov,i);
12013 // Beginning of automatic outputs (from unused autoinst outputs)
12014 output [31:0] ov; // From inst of inst.v
12015 // End of automatics
12016 InstModule instName
12024 You may also provide an optional regular expression, in which case only
12025 signals matching the regular expression will be included. For example the
12026 same expansion will result from only extracting outputs starting with ov:
12028 /*AUTOOUTPUT(\"^ov\")*/"
12030 ;; Point must be at insertion point.
12031 (let* ((indent-pt (current-indentation))
12032 (params (verilog-read-auto-params 0 1))
12033 (regexp (nth 0 params))
12034 (v2k (verilog-in-paren-quick))
12035 (modi (verilog-modi-current))
12036 (moddecls (verilog-modi-get-decls modi))
12037 (modsubdecls (verilog-modi-get-sub-decls modi))
12038 (sig-list (verilog-signals-not-in
12039 (verilog-subdecls-get-outputs modsubdecls)
12040 (append (verilog-decls-get-outputs moddecls)
12041 (verilog-decls-get-inouts moddecls)
12042 (verilog-decls-get-inputs moddecls)
12043 (verilog-subdecls-get-inputs modsubdecls)
12044 (verilog-subdecls-get-inouts modsubdecls)))))
12046 (setq sig-list (verilog-signals-matching-regexp
12048 (setq sig-list (verilog-signals-not-matching-regexp
12049 sig-list verilog-auto-output-ignore-regexp))
12050 (verilog-forward-or-insert-line)
12051 (when v2k (verilog-repair-open-comma))
12053 (verilog-insert-indent "// Beginning of automatic outputs (from unused autoinst outputs)\n")
12054 (verilog-insert-definition modi sig-list "output" indent-pt v2k)
12055 (verilog-insert-indent "// End of automatics\n"))
12056 (when v2k (verilog-repair-close-comma)))))
12058 (defun verilog-auto-output-every ()
12059 "Expand AUTOOUTPUTEVERY statements, as part of \\[verilog-auto].
12060 Make output statements for any signals that aren't primary inputs or
12061 outputs already. This makes every signal in the design an output. This is
12062 useful to get Synopsys to preserve every signal in the design, since it
12063 won't optimize away the outputs.
12067 module ExampOutputEvery (o,i,tempa,tempb);
12070 /*AUTOOUTPUTEVERY*/
12072 wire tempb = tempa;
12076 Typing \\[verilog-auto] will make this into:
12078 module ExampOutputEvery (o,i,tempa,tempb);
12081 /*AUTOOUTPUTEVERY*/
12082 // Beginning of automatic outputs (every signal)
12085 // End of automatics
12087 wire tempb = tempa;
12091 You may also provide an optional regular expression, in which case only
12092 signals matching the regular expression will be included. For example the
12093 same expansion will result from only extracting outputs starting with ov:
12095 /*AUTOOUTPUTEVERY(\"^ov\")*/"
12097 ;;Point must be at insertion point
12098 (let* ((indent-pt (current-indentation))
12099 (params (verilog-read-auto-params 0 1))
12100 (regexp (nth 0 params))
12101 (v2k (verilog-in-paren-quick))
12102 (modi (verilog-modi-current))
12103 (moddecls (verilog-modi-get-decls modi))
12104 (sig-list (verilog-signals-combine-bus
12105 (verilog-signals-not-in
12106 (verilog-decls-get-signals moddecls)
12107 (verilog-decls-get-ports moddecls)))))
12109 (setq sig-list (verilog-signals-matching-regexp
12111 (setq sig-list (verilog-signals-not-matching-regexp
12112 sig-list verilog-auto-output-ignore-regexp))
12113 (verilog-forward-or-insert-line)
12114 (when v2k (verilog-repair-open-comma))
12116 (verilog-insert-indent "// Beginning of automatic outputs (every signal)\n")
12117 (verilog-insert-definition modi sig-list "output" indent-pt v2k)
12118 (verilog-insert-indent "// End of automatics\n"))
12119 (when v2k (verilog-repair-close-comma)))))
12121 (defun verilog-auto-input ()
12122 "Expand AUTOINPUT statements, as part of \\[verilog-auto].
12123 Make input statements for any input signal into an /*AUTOINST*/ that
12124 isn't declared elsewhere inside the module. This is useful for modules which
12125 only instantiate other modules.
12128 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
12130 If placed inside the parenthesis of a module declaration, it creates
12131 Verilog 2001 style, else uses Verilog 1995 style.
12133 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
12134 instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
12136 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
12138 Types are added to declarations if an AUTOLOGIC or
12139 `verilog-auto-wire-type' is set to logic.
12141 Signals matching `verilog-auto-input-ignore-regexp' are not included.
12143 An example (see `verilog-auto-inst' for what else is going on here):
12145 module ExampInput (ov,i);
12148 InstModule instName
12152 Typing \\[verilog-auto] will make this into:
12154 module ExampInput (ov,i);
12157 // Beginning of automatic inputs (from unused autoinst inputs)
12158 input i; // From inst of inst.v
12159 // End of automatics
12160 InstModule instName
12168 You may also provide an optional regular expression, in which case only
12169 signals matching the regular expression will be included. For example the
12170 same expansion will result from only extracting inputs starting with i:
12172 /*AUTOINPUT(\"^i\")*/"
12174 (let* ((indent-pt (current-indentation))
12175 (params (verilog-read-auto-params 0 1))
12176 (regexp (nth 0 params))
12177 (v2k (verilog-in-paren-quick))
12178 (modi (verilog-modi-current))
12179 (moddecls (verilog-modi-get-decls modi))
12180 (modsubdecls (verilog-modi-get-sub-decls modi))
12181 (sig-list (verilog-signals-not-in
12182 (verilog-subdecls-get-inputs modsubdecls)
12183 (append (verilog-decls-get-inputs moddecls)
12184 (verilog-decls-get-inouts moddecls)
12185 (verilog-decls-get-outputs moddecls)
12186 (verilog-decls-get-vars moddecls)
12187 (verilog-decls-get-consts moddecls)
12188 (verilog-decls-get-gparams moddecls)
12189 (verilog-subdecls-get-interfaced modsubdecls)
12190 (verilog-subdecls-get-outputs modsubdecls)
12191 (verilog-subdecls-get-inouts modsubdecls)))))
12193 (setq sig-list (verilog-signals-matching-regexp
12195 (setq sig-list (verilog-signals-not-matching-regexp
12196 sig-list verilog-auto-input-ignore-regexp))
12197 (verilog-forward-or-insert-line)
12198 (when v2k (verilog-repair-open-comma))
12200 (verilog-insert-indent "// Beginning of automatic inputs (from unused autoinst inputs)\n")
12201 (verilog-insert-definition modi sig-list "input" indent-pt v2k)
12202 (verilog-insert-indent "// End of automatics\n"))
12203 (when v2k (verilog-repair-close-comma)))))
12205 (defun verilog-auto-inout ()
12206 "Expand AUTOINOUT statements, as part of \\[verilog-auto].
12207 Make inout statements for any inout signal in an /*AUTOINST*/ that
12208 isn't declared elsewhere inside the module.
12211 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
12213 If placed inside the parenthesis of a module declaration, it creates
12214 Verilog 2001 style, else uses Verilog 1995 style.
12216 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
12217 instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
12219 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
12221 Types are added to declarations if an AUTOLOGIC or
12222 `verilog-auto-wire-type' is set to logic.
12224 Signals matching `verilog-auto-inout-ignore-regexp' are not included.
12226 An example (see `verilog-auto-inst' for what else is going on here):
12228 module ExampInout (ov,i);
12231 InstModule instName
12235 Typing \\[verilog-auto] will make this into:
12237 module ExampInout (ov,i);
12240 // Beginning of automatic inouts (from unused autoinst inouts)
12241 inout [31:0] ov; // From inst of inst.v
12242 // End of automatics
12243 InstModule instName
12251 You may also provide an optional regular expression, in which case only
12252 signals matching the regular expression will be included. For example the
12253 same expansion will result from only extracting inouts starting with i:
12255 /*AUTOINOUT(\"^i\")*/"
12257 ;; Point must be at insertion point.
12258 (let* ((indent-pt (current-indentation))
12259 (params (verilog-read-auto-params 0 1))
12260 (regexp (nth 0 params))
12261 (v2k (verilog-in-paren-quick))
12262 (modi (verilog-modi-current))
12263 (moddecls (verilog-modi-get-decls modi))
12264 (modsubdecls (verilog-modi-get-sub-decls modi))
12265 (sig-list (verilog-signals-not-in
12266 (verilog-subdecls-get-inouts modsubdecls)
12267 (append (verilog-decls-get-outputs moddecls)
12268 (verilog-decls-get-inouts moddecls)
12269 (verilog-decls-get-inputs moddecls)
12270 (verilog-subdecls-get-inputs modsubdecls)
12271 (verilog-subdecls-get-outputs modsubdecls)))))
12273 (setq sig-list (verilog-signals-matching-regexp
12275 (setq sig-list (verilog-signals-not-matching-regexp
12276 sig-list verilog-auto-inout-ignore-regexp))
12277 (verilog-forward-or-insert-line)
12278 (when v2k (verilog-repair-open-comma))
12280 (verilog-insert-indent "// Beginning of automatic inouts (from unused autoinst inouts)\n")
12281 (verilog-insert-definition modi sig-list "inout" indent-pt v2k)
12282 (verilog-insert-indent "// End of automatics\n"))
12283 (when v2k (verilog-repair-close-comma)))))
12285 (defun verilog-auto-inout-module (&optional complement all-in)
12286 "Expand AUTOINOUTMODULE statements, as part of \\[verilog-auto].
12287 Take input/output/inout statements from the specified module and insert
12288 into the current module. This is useful for making null templates and
12289 shell modules which need to have identical I/O with another module.
12290 Any I/O which are already defined in this module will not be redefined.
12291 For the complement of this function, see `verilog-auto-inout-comp',
12292 and to make monitors with all inputs, see `verilog-auto-inout-in'.
12295 If placed inside the parenthesis of a module declaration, it creates
12296 Verilog 2001 style, else uses Verilog 1995 style.
12298 Concatenation and outputting partial buses is not supported.
12300 Module names must be resolvable to filenames. See `verilog-auto-inst'.
12302 Signals are not inserted in the same order as in the original module,
12303 though they will appear to be in the same order to an AUTOINST
12304 instantiating either module.
12306 Signals declared as \"output reg\" or \"output wire\" etc will
12307 lose the wire/reg declaration so that shell modules may
12308 generate those outputs differently. However, \"output logic\"
12313 module ExampShell (/*AUTOARG*/);
12314 /*AUTOINOUTMODULE(\"ExampMain\")*/
12317 module ExampMain (i,o,io);
12323 Typing \\[verilog-auto] will make this into:
12325 module ExampShell (/*AUTOARG*/i,o,io);
12326 /*AUTOINOUTMODULE(\"ExampMain\")*/
12327 // Beginning of automatic in/out/inouts (from specific module)
12331 // End of automatics
12334 You may also provide an optional regular expression, in which case only
12335 signals matching the regular expression will be included. For example the
12336 same expansion will result from only extracting signals starting with i:
12338 /*AUTOINOUTMODULE(\"ExampMain\",\"^i\")*/
12340 You may also provide an optional third argument regular
12341 expression, in which case only signals which have that pin
12342 direction and data type matching that regular expression will be
12343 included. This matches against everything before the signal name
12344 in the declaration, for example against \"input\" (single
12345 bit), \"output logic\" (direction and type) or
12346 \"output [1:0]\" (direction and implicit type). You also
12347 probably want to skip spaces in your regexp.
12349 For example, the below will result in matching the output \"o\"
12350 against the previous example's module:
12352 /*AUTOINOUTMODULE(\"ExampMain\",\"\",\"^output.*\")*/
12354 You may also provide an optional fourth argument regular
12355 expression, which if not \"\" only signals which do NOT match
12356 that expression are included."
12357 ;; Beware spacing of quotes in above as can mess up Emacs indenter
12359 (let* ((params (verilog-read-auto-params 1 4))
12360 (submod (nth 0 params))
12361 (regexp (nth 1 params))
12362 (direction-re (nth 2 params))
12363 (not-re (nth 3 params))
12365 ;; Lookup position, etc of co-module
12366 ;; Note this may raise an error
12367 (when (setq submodi (verilog-modi-lookup submod t))
12368 (let* ((indent-pt (current-indentation))
12369 (v2k (verilog-in-paren-quick))
12370 (modi (verilog-modi-current))
12371 (moddecls (verilog-modi-get-decls modi))
12372 (submoddecls (verilog-modi-get-decls submodi))
12373 (sig-list-i (verilog-signals-not-in
12376 (verilog-decls-get-inputs submoddecls)
12377 (verilog-decls-get-inouts submoddecls)
12378 (verilog-decls-get-outputs submoddecls)))
12380 (verilog-decls-get-outputs submoddecls))
12381 (t (verilog-decls-get-inputs submoddecls)))
12382 (append (verilog-decls-get-inputs moddecls))))
12383 (sig-list-o (verilog-signals-not-in
12386 (verilog-decls-get-inputs submoddecls))
12387 (t (verilog-decls-get-outputs submoddecls)))
12388 (append (verilog-decls-get-outputs moddecls))))
12389 (sig-list-io (verilog-signals-not-in
12391 (t (verilog-decls-get-inouts submoddecls)))
12392 (append (verilog-decls-get-inouts moddecls))))
12393 (sig-list-if (verilog-signals-not-in
12394 (verilog-decls-get-interfaces submoddecls)
12395 (append (verilog-decls-get-interfaces moddecls)))))
12397 (setq sig-list-i (verilog-signals-edit-wire-reg
12398 (verilog-signals-not-matching-regexp
12399 (verilog-signals-matching-dir-re
12400 (verilog-signals-matching-regexp sig-list-i regexp)
12401 "input" direction-re) not-re))
12402 sig-list-o (verilog-signals-edit-wire-reg
12403 (verilog-signals-not-matching-regexp
12404 (verilog-signals-matching-dir-re
12405 (verilog-signals-matching-regexp sig-list-o regexp)
12406 "output" direction-re) not-re))
12407 sig-list-io (verilog-signals-edit-wire-reg
12408 (verilog-signals-not-matching-regexp
12409 (verilog-signals-matching-dir-re
12410 (verilog-signals-matching-regexp sig-list-io regexp)
12411 "inout" direction-re) not-re))
12412 sig-list-if (verilog-signals-not-matching-regexp
12413 (verilog-signals-matching-dir-re
12414 (verilog-signals-matching-regexp sig-list-if regexp)
12415 "interface" direction-re) not-re))
12416 (when v2k (verilog-repair-open-comma))
12417 (when (or sig-list-i sig-list-o sig-list-io sig-list-if)
12418 (verilog-insert-indent "// Beginning of automatic in/out/inouts (from specific module)\n")
12419 ;; Don't sort them so an upper AUTOINST will match the main module
12420 (verilog-insert-definition modi sig-list-o "output" indent-pt v2k t)
12421 (verilog-insert-definition modi sig-list-io "inout" indent-pt v2k t)
12422 (verilog-insert-definition modi sig-list-i "input" indent-pt v2k t)
12423 (verilog-insert-definition modi sig-list-if "interface" indent-pt v2k t)
12424 (verilog-insert-indent "// End of automatics\n"))
12425 (when v2k (verilog-repair-close-comma)))))))
12427 (defun verilog-auto-inout-comp ()
12428 "Expand AUTOINOUTCOMP statements, as part of \\[verilog-auto].
12429 Take input/output/inout statements from the specified module and
12430 insert the inverse into the current module (inputs become outputs
12431 and vice-versa.) This is useful for making test and stimulus
12432 modules which need to have complementing I/O with another module.
12433 Any I/O which are already defined in this module will not be
12434 redefined. For the complement of this function, see
12435 `verilog-auto-inout-module'.
12438 If placed inside the parenthesis of a module declaration, it creates
12439 Verilog 2001 style, else uses Verilog 1995 style.
12441 Concatenation and outputting partial buses is not supported.
12443 Module names must be resolvable to filenames. See `verilog-auto-inst'.
12445 Signals are not inserted in the same order as in the original module,
12446 though they will appear to be in the same order to an AUTOINST
12447 instantiating either module.
12451 module ExampShell (/*AUTOARG*/);
12452 /*AUTOINOUTCOMP(\"ExampMain\")*/
12455 module ExampMain (i,o,io);
12461 Typing \\[verilog-auto] will make this into:
12463 module ExampShell (/*AUTOARG*/i,o,io);
12464 /*AUTOINOUTCOMP(\"ExampMain\")*/
12465 // Beginning of automatic in/out/inouts (from specific module)
12469 // End of automatics
12472 You may also provide an optional regular expression, in which case only
12473 signals matching the regular expression will be included. For example the
12474 same expansion will result from only extracting signals starting with i:
12476 /*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/
12478 You may also provide an optional third argument regular
12479 expression, in which case only signals which have that pin
12480 direction and data type matching that regular expression will be
12481 included. This matches against everything before the signal name
12482 in the declaration, for example against \"input\" (single
12483 bit), \"output logic\" (direction and type)
12484 or \"output [1:0]\" (direction and implicit type). You also
12485 probably want to skip spaces in your regexp.
12487 For example, the below will result in matching the output \"o\"
12488 against the previous example's module:
12490 /*AUTOINOUTCOMP(\"ExampMain\",\"\",\"^output.*\")*/
12492 You may also provide an optional fourth argument regular
12493 expression, which if not \"\" only signals which do NOT match
12494 that expression are included."
12495 ;; Beware spacing of quotes in above as can mess up Emacs indenter
12496 (verilog-auto-inout-module t nil))
12498 (defun verilog-auto-inout-in ()
12499 "Expand AUTOINOUTIN statements, as part of \\[verilog-auto].
12500 Take input/output/inout statements from the specified module and
12501 insert them as all inputs into the current module. This is
12502 useful for making monitor modules which need to see all signals
12503 as inputs based on another module. Any I/O which are already
12504 defined in this module will not be redefined. See also
12505 `verilog-auto-inout-module'.
12508 If placed inside the parenthesis of a module declaration, it creates
12509 Verilog 2001 style, else uses Verilog 1995 style.
12511 Concatenation and outputting partial buses is not supported.
12513 Module names must be resolvable to filenames. See `verilog-auto-inst'.
12515 Signals are not inserted in the same order as in the original module,
12516 though they will appear to be in the same order to an AUTOINST
12517 instantiating either module.
12521 module ExampShell (/*AUTOARG*/);
12522 /*AUTOINOUTIN(\"ExampMain\")*/
12525 module ExampMain (i,o,io);
12531 Typing \\[verilog-auto] will make this into:
12533 module ExampShell (/*AUTOARG*/i,o,io);
12534 /*AUTOINOUTIN(\"ExampMain\")*/
12535 // Beginning of automatic in/out/inouts (from specific module)
12539 // End of automatics
12542 You may also provide an optional regular expression, in which case only
12543 signals matching the regular expression will be included. For example the
12544 same expansion will result from only extracting signals starting with i:
12546 /*AUTOINOUTIN(\"ExampMain\",\"^i\")*/"
12547 (verilog-auto-inout-module nil t))
12549 (defun verilog-auto-inout-param ()
12550 "Expand AUTOINOUTPARAM statements, as part of \\[verilog-auto].
12551 Take input/output/inout statements from the specified module and insert
12552 into the current module. This is useful for making null templates and
12553 shell modules which need to have identical I/O with another module.
12554 Any I/O which are already defined in this module will not be redefined.
12555 For the complement of this function, see `verilog-auto-inout-comp',
12556 and to make monitors with all inputs, see `verilog-auto-inout-in'.
12559 If placed inside the parenthesis of a module declaration, it creates
12560 Verilog 2001 style, else uses Verilog 1995 style.
12562 Module names must be resolvable to filenames. See `verilog-auto-inst'.
12564 Parameters are inserted in the same order as in the original module.
12566 Parameters do not have values, which is SystemVerilog 2009 syntax.
12570 module ExampShell ();
12571 /*AUTOINOUTPARAM(\"ExampMain\")*/
12574 module ExampMain ();
12575 parameter PARAM = 22;
12578 Typing \\[verilog-auto] will make this into:
12580 module ExampShell (/*AUTOARG*/i,o,io);
12581 /*AUTOINOUTPARAM(\"ExampMain\")*/
12582 // Beginning of automatic parameters (from specific module)
12584 // End of automatics
12587 You may also provide an optional regular expression, in which case only
12588 parameters matching the regular expression will be included. For example the
12589 same expansion will result from only extracting parameters starting with i:
12591 /*AUTOINOUTPARAM(\"ExampMain\",\"^i\")*/"
12593 (let* ((params (verilog-read-auto-params 1 2))
12594 (submod (nth 0 params))
12595 (regexp (nth 1 params))
12597 ;; Lookup position, etc of co-module
12598 ;; Note this may raise an error
12599 (when (setq submodi (verilog-modi-lookup submod t))
12600 (let* ((indent-pt (current-indentation))
12601 (v2k (verilog-in-paren-quick))
12602 (modi (verilog-modi-current))
12603 (moddecls (verilog-modi-get-decls modi))
12604 (submoddecls (verilog-modi-get-decls submodi))
12605 (sig-list-p (verilog-signals-not-in
12606 (verilog-decls-get-gparams submoddecls)
12607 (append (verilog-decls-get-gparams moddecls)))))
12609 (setq sig-list-p (verilog-signals-matching-regexp sig-list-p regexp))
12610 (when v2k (verilog-repair-open-comma))
12612 (verilog-insert-indent "// Beginning of automatic parameters (from specific module)\n")
12613 ;; Don't sort them so an upper AUTOINST will match the main module
12614 (verilog-insert-definition modi sig-list-p "parameter" indent-pt v2k t)
12615 (verilog-insert-indent "// End of automatics\n"))
12616 (when v2k (verilog-repair-close-comma)))))))
12618 (defun verilog-auto-inout-modport ()
12619 "Expand AUTOINOUTMODPORT statements, as part of \\[verilog-auto].
12620 Take input/output/inout statements from the specified interface
12621 and modport and insert into the current module. This is useful
12622 for making verification modules that connect to UVM interfaces.
12624 The first parameter is the name of an interface.
12626 The second parameter is a regexp of modports to read from in
12629 The optional third parameter is a regular expression, and only
12630 signals matching the regular expression will be included.
12633 If placed inside the parenthesis of a module declaration, it creates
12634 Verilog 2001 style, else uses Verilog 1995 style.
12636 Interface names must be resolvable to filenames. See `verilog-auto-inst'.
12638 As with other autos, any inputs/outputs declared in the module
12639 will suppress the AUTO from redeclaring an inputs/outputs by
12645 ( input logic clk );
12647 logic [7:0] req_dat;
12648 clocking mon_clkblk @(posedge clk);
12652 modport mp(clocking mon_clkblk);
12657 /*AUTOINOUTMODPORT(\"ExampIf\" \"mp\")*/
12658 // Beginning of automatic in/out/inouts (from modport)
12659 input [7:0] req_dat,
12661 // End of automatics
12663 /*AUTOASSIGNMODPORT(\"ExampIf\" \"mp\")*/
12666 Typing \\[verilog-auto] will make this into:
12671 /*AUTOINOUTMODPORT(\"ExampIf\" \"mp\")*/
12672 // Beginning of automatic in/out/inouts (from modport)
12675 // End of automatics
12678 If the modport is part of a UVM monitor/driver class, this
12679 creates a wrapper module that may be used to instantiate the
12680 driver/monitor using AUTOINST in the testbench."
12682 (let* ((params (verilog-read-auto-params 2 3))
12683 (submod (nth 0 params))
12684 (modport-re (nth 1 params))
12685 (regexp (nth 2 params))
12686 direction-re submodi) ; direction argument not supported until requested
12687 ;; Lookup position, etc of co-module
12688 ;; Note this may raise an error
12689 (when (setq submodi (verilog-modi-lookup submod t))
12690 (let* ((indent-pt (current-indentation))
12691 (v2k (verilog-in-paren-quick))
12692 (modi (verilog-modi-current))
12693 (moddecls (verilog-modi-get-decls modi))
12694 (submoddecls (verilog-modi-get-decls submodi))
12695 (submodportdecls (verilog-modi-modport-lookup submodi modport-re))
12696 (sig-list-i (verilog-signals-in ; Decls doesn't have data types, must resolve
12697 (verilog-decls-get-vars submoddecls)
12698 (verilog-signals-not-in
12699 (verilog-decls-get-inputs submodportdecls)
12700 (append (verilog-decls-get-ports submoddecls)
12701 (verilog-decls-get-ports moddecls)))))
12702 (sig-list-o (verilog-signals-in ; Decls doesn't have data types, must resolve
12703 (verilog-decls-get-vars submoddecls)
12704 (verilog-signals-not-in
12705 (verilog-decls-get-outputs submodportdecls)
12706 (append (verilog-decls-get-ports submoddecls)
12707 (verilog-decls-get-ports moddecls)))))
12708 (sig-list-io (verilog-signals-in ; Decls doesn't have data types, must resolve
12709 (verilog-decls-get-vars submoddecls)
12710 (verilog-signals-not-in
12711 (verilog-decls-get-inouts submodportdecls)
12712 (append (verilog-decls-get-ports submoddecls)
12713 (verilog-decls-get-ports moddecls))))))
12715 (setq sig-list-i (verilog-signals-edit-wire-reg
12716 (verilog-signals-matching-dir-re
12717 (verilog-signals-matching-regexp sig-list-i regexp)
12718 "input" direction-re))
12719 sig-list-o (verilog-signals-edit-wire-reg
12720 (verilog-signals-matching-dir-re
12721 (verilog-signals-matching-regexp sig-list-o regexp)
12722 "output" direction-re))
12723 sig-list-io (verilog-signals-edit-wire-reg
12724 (verilog-signals-matching-dir-re
12725 (verilog-signals-matching-regexp sig-list-io regexp)
12726 "inout" direction-re)))
12727 (when v2k (verilog-repair-open-comma))
12728 (when (or sig-list-i sig-list-o sig-list-io)
12729 (verilog-insert-indent "// Beginning of automatic in/out/inouts (from modport)\n")
12730 ;; Don't sort them so an upper AUTOINST will match the main module
12731 (verilog-insert-definition modi sig-list-o "output" indent-pt v2k t)
12732 (verilog-insert-definition modi sig-list-io "inout" indent-pt v2k t)
12733 (verilog-insert-definition modi sig-list-i "input" indent-pt v2k t)
12734 (verilog-insert-indent "// End of automatics\n"))
12735 (when v2k (verilog-repair-close-comma)))))))
12737 (defun verilog-auto-insert-lisp ()
12738 "Expand AUTOINSERTLISP statements, as part of \\[verilog-auto].
12739 The Lisp code provided is called before other AUTOS are expanded,
12740 and the Lisp code generally will call `insert' to insert text
12741 into the current file beginning on the line after the
12744 See also AUTOINSERTLAST and `verilog-auto-insert-last' which
12745 executes after (as opposed to before) other AUTOs.
12747 See also AUTO_LISP, which takes a Lisp expression and evaluates
12748 it during `verilog-auto-inst' but does not insert any text.
12752 module ExampInsertLisp;
12753 /*AUTOINSERTLISP(my-verilog-insert-hello \"world\")*/
12756 // For this example we declare the function in the
12757 // module's file itself. Often you'd define it instead
12758 // in a site-start.el or init file.
12762 (defun my-verilog-insert-hello (who)
12763 (insert (concat \"initial $write(\\\"hello \" who \"\\\");\\n\")))
12767 Typing \\[verilog-auto] will call my-verilog-insert-hello and
12768 expand the above into:
12770 // Beginning of automatic insert lisp
12771 initial $write(\"hello world\");
12772 // End of automatics
12774 You can also call an external program and insert the returned
12777 /*AUTOINSERTLISP(insert (shell-command-to-string \"echo //hello\"))*/
12778 // Beginning of automatic insert lisp
12780 // End of automatics"
12782 ;; Point is at end of /*AUTO...*/
12783 (let* ((indent-pt (current-indentation))
12784 (cmd-end-pt (save-excursion (search-backward ")")
12786 (point))) ; Closing paren
12787 (cmd-beg-pt (save-excursion (goto-char cmd-end-pt)
12788 (backward-sexp 1) ; Inside comment
12789 (point))) ; Beginning paren
12790 (cmd (buffer-substring-no-properties cmd-beg-pt cmd-end-pt)))
12791 (verilog-forward-or-insert-line)
12792 ;; Some commands don't move point (like insert-file) so we always
12793 ;; add the begin/end comments, then delete it if not needed
12794 (verilog-insert-indent "// Beginning of automatic insert lisp\n")
12795 (verilog-insert-indent "// End of automatics\n")
12799 (setq verilog-scan-cache-tick nil) ; Clear cache; inserted unknown text
12800 (verilog-delete-empty-auto-pair))))
12802 (defun verilog-auto-insert-last ()
12803 "Expand AUTOINSERTLAST statements, as part of \\[verilog-auto].
12804 The Lisp code provided is called after all other AUTOS have been
12805 expanded, and the Lisp code generally will call `insert' to
12806 insert text into the current file beginning on the line after the
12809 Other than when called (after AUTOs are expanded), the functionality
12810 is otherwise identical to AUTOINSERTLISP and `verilog-auto-insert-lisp' which
12811 executes before (as opposed to after) other AUTOs.
12813 See `verilog-auto-insert-lisp' for examples."
12814 (verilog-auto-insert-lisp))
12816 (defun verilog-auto-sense-sigs (moddecls presense-sigs)
12817 "Return list of signals for current AUTOSENSE block."
12818 (let* ((sigss (save-excursion
12819 (search-forward ")")
12820 (verilog-read-always-signals)))
12821 (sig-list (verilog-signals-not-params
12822 (verilog-signals-not-in (verilog-alw-get-inputs sigss)
12823 (append (and (not verilog-auto-sense-include-inputs)
12824 (verilog-alw-get-outputs-delayed sigss))
12825 (and (not verilog-auto-sense-include-inputs)
12826 (verilog-alw-get-outputs-immediate sigss))
12827 (verilog-alw-get-temps sigss)
12828 (verilog-decls-get-consts moddecls)
12829 (verilog-decls-get-gparams moddecls)
12833 (defun verilog-auto-sense ()
12834 "Expand AUTOSENSE statements, as part of \\[verilog-auto].
12835 Replace the always (/*AUTOSENSE*/) sensitivity list (/*AS*/ for short)
12836 with one automatically derived from all inputs declared in the always
12837 statement. Signals that are generated within the same always block are NOT
12838 placed into the sensitivity list (see `verilog-auto-sense-include-inputs').
12839 Long lines are split based on the `fill-column', see \\[set-fill-column].
12842 Verilog does not allow memories (multidimensional arrays) in sensitivity
12843 lists. AUTOSENSE will thus exclude them, and add a /*memory or*/ comment.
12846 AUTOSENSE cannot always determine if a \\=`define is a constant or a signal
12847 (it could be in an include file for example). If a \\=`define or other signal
12848 is put into the AUTOSENSE list and is not desired, use the AUTO_CONSTANT
12849 declaration anywhere in the module (parenthesis are required):
12851 /* AUTO_CONSTANT ( \\=`this_is_really_constant_dont_autosense_it ) */
12853 Better yet, use a parameter, which will be understood to be constant
12857 If AUTOSENSE makes a mistake, please report it. (First try putting
12858 a begin/end after your always!) As a workaround, if a signal that
12859 shouldn't be in the sensitivity list was, use the AUTO_CONSTANT above.
12860 If a signal should be in the sensitivity list wasn't, placing it before
12861 the /*AUTOSENSE*/ comment will prevent it from being deleted when the
12862 autos are updated (or added if it occurs there already).
12866 always @ (/*AS*/) begin
12867 /* AUTO_CONSTANT (\\=`constant) */
12868 outin = ina | inb | \\=`constant;
12872 Typing \\[verilog-auto] will make this into:
12874 always @ (/*AS*/ina or inb) begin
12875 /* AUTO_CONSTANT (\\=`constant) */
12876 outin = ina | inb | \\=`constant;
12880 Note in Verilog 2001, you can often get the same result from the new @*
12881 operator. (This was added to the language in part due to AUTOSENSE!)
12884 outin = ina | inb | \\=`constant;
12889 (let* ((start-pt (save-excursion
12890 (verilog-re-search-backward-quick "(" nil t)
12892 (indent-pt (save-excursion
12893 (or (and (goto-char start-pt) (1+ (current-column)))
12894 (current-indentation))))
12895 (modi (verilog-modi-current))
12896 (moddecls (verilog-modi-get-decls modi))
12897 (sig-memories (verilog-signals-memory
12898 (verilog-decls-get-vars moddecls)))
12899 sig-list not-first presense-sigs)
12900 ;; Read signals in always, eliminate outputs from sense list
12901 (setq presense-sigs (verilog-signals-from-signame
12903 (verilog-read-signals start-pt (point)))))
12904 (setq sig-list (verilog-auto-sense-sigs moddecls presense-sigs))
12906 (let ((tlen (length sig-list)))
12907 (setq sig-list (verilog-signals-not-in sig-list sig-memories))
12908 (if (not (eq tlen (length sig-list))) (verilog-insert " /*memory or*/ "))))
12909 (if (and presense-sigs ; Add a "or" if not "(.... or /*AUTOSENSE*/"
12910 (save-excursion (goto-char (point))
12911 (verilog-re-search-backward-quick "[a-zA-Z0-9$_.%`]+" start-pt t)
12912 (verilog-re-search-backward-quick "\\s-" start-pt t)
12913 (while (looking-at "\\s-`endif")
12914 (verilog-re-search-backward-quick "[a-zA-Z0-9$_.%`]+" start-pt t)
12915 (verilog-re-search-backward-quick "\\s-" start-pt t))
12916 (not (looking-at "\\s-or\\b"))))
12917 (setq not-first t))
12918 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
12920 (cond ((> (+ 4 (current-column) (length (verilog-sig-name (car sig-list)))) fill-column) ;+4 for width of or
12922 (indent-to indent-pt)
12923 (if not-first (insert "or ")))
12924 (not-first (insert " or ")))
12925 (insert (verilog-sig-name (car sig-list)))
12926 (setq sig-list (cdr sig-list)
12929 (defun verilog-auto-reset ()
12930 "Expand AUTORESET statements, as part of \\[verilog-auto].
12931 Replace the /*AUTORESET*/ comment with code to initialize all
12932 registers set elsewhere in the always block.
12935 AUTORESET will not clear memories.
12937 AUTORESET uses <= if the signal has a <= assignment in the block,
12940 If <= is used, all = assigned variables are ignored if
12941 `verilog-auto-reset-blocking-in-non' is nil; they are presumed
12944 /*AUTORESET*/ presumes that any signals mentioned between the previous
12945 begin/case/if statement and the AUTORESET comment are being reset manually
12946 and should not be automatically reset. This includes omitting any signals
12947 used on the right hand side of assignments.
12949 By default, AUTORESET will include the width of the signal in the
12950 autos, SystemVerilog designs may want to change this. To control
12951 this behavior, see `verilog-auto-reset-widths'. In some cases
12952 AUTORESET must use a \\='0 assignment and it will print NOWIDTH; use
12953 `verilog-auto-reset-widths' unbased to prevent this.
12955 AUTORESET ties signals to deasserted, which is presumed to be zero.
12956 Signals that match `verilog-active-low-regexp' will be deasserted by tying
12959 AUTORESET may try to reset arrays or structures that cannot be
12960 reset by a simple assignment, resulting in compile errors. This
12961 is a feature to be taken as a hint that you need to reset these
12962 signals manually (or put them into a \"\\=`ifdef NEVER signal<=\\=`0;
12963 \\=`endif\" so Verilog-Mode ignores them.)
12967 always @(posedge clk or negedge reset_l) begin
12968 if (!reset_l) begin
12979 Typing \\[verilog-auto] will make this into:
12981 always @(posedge core_clk or negedge reset_l) begin
12982 if (!reset_l) begin
12985 // Beginning of autoreset for uninitialized flops
12987 b = 0; // if `verilog-auto-reset-blocking-in-non' true
12988 // End of automatics
13000 (let* ((indent-pt (current-indentation))
13001 (modi (verilog-modi-current))
13002 (moddecls (verilog-modi-get-decls modi))
13003 (all-list (verilog-decls-get-signals moddecls))
13004 sigss sig-list dly-list prereset-sigs)
13005 ;; Read signals in always, eliminate outputs from reset list
13006 (setq prereset-sigs (verilog-signals-from-signame
13008 (verilog-read-signals
13010 (verilog-re-search-backward-quick
13011 "\\(@\\|\\<\\(begin\\|if\\|case\\|always\\(_latch\\|_ff\\|_comb\\)?\\)\\>\\)" nil t)
13015 (verilog-re-search-backward-quick "\\(@\\|\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\)\\>\\)" nil t)
13016 (setq sigss (verilog-read-always-signals)))
13017 (setq dly-list (verilog-alw-get-outputs-delayed sigss))
13018 (setq sig-list (verilog-signals-not-in-struct
13020 (verilog-alw-get-outputs-delayed sigss)
13021 (when (or (not (verilog-alw-get-uses-delayed sigss))
13022 verilog-auto-reset-blocking-in-non)
13023 (verilog-alw-get-outputs-immediate sigss)))
13025 (verilog-alw-get-temps sigss)
13027 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
13030 (verilog-insert-indent "// Beginning of autoreset for uninitialized flops\n");
13032 (let ((sig (or (assoc (verilog-sig-name (car sig-list)) all-list) ; As sig-list has no widths
13034 (indent-to indent-pt)
13035 (insert (verilog-sig-name sig)
13036 (if (assoc (verilog-sig-name sig) dly-list)
13037 (concat " <= " verilog-assignment-delay)
13039 (verilog-sig-tieoff sig)
13041 (setq sig-list (cdr sig-list))))
13042 (verilog-insert-indent "// End of automatics")))))
13044 (defun verilog-auto-tieoff ()
13045 "Expand AUTOTIEOFF statements, as part of \\[verilog-auto].
13046 Replace the /*AUTOTIEOFF*/ comment with code to wire-tie all unused output
13047 signals to deasserted.
13049 /*AUTOTIEOFF*/ is used to make stub modules; modules that have the same
13050 input/output list as another module, but no internals. Specifically, it
13051 finds all outputs in the module, and if that input is not otherwise declared
13052 as a register or wire, creates a tieoff.
13054 AUTORESET ties signals to deasserted, which is presumed to be zero.
13055 Signals that match `verilog-active-low-regexp' will be deasserted by tying
13058 You can add signals you do not want included in AUTOTIEOFF with
13059 `verilog-auto-tieoff-ignore-regexp'.
13061 `verilog-auto-wire-type' may be used to change the datatype of
13064 `verilog-auto-reset-widths' may be used to change how the tieoff
13065 value's width is generated.
13067 An example of making a stub for another module:
13069 module ExampStub (/*AUTOINST*/);
13070 /*AUTOINOUTPARAM(\"Foo\")*/
13071 /*AUTOINOUTMODULE(\"Foo\")*/
13073 // verilator lint_off UNUSED
13074 wire _unused_ok = &{1\\='b0,
13077 // verilator lint_on UNUSED
13080 Typing \\[verilog-auto] will make this into:
13082 module ExampStub (/*AUTOINST*/...);
13083 /*AUTOINOUTPARAM(\"Foo\")*/
13084 /*AUTOINOUTMODULE(\"Foo\")*/
13085 // Beginning of autotieoff
13087 // End of automatics
13090 // Beginning of autotieoff
13091 wire [2:0] foo = 3\\='b0;
13092 // End of automatics
13098 (let* ((indent-pt (current-indentation))
13099 (modi (verilog-modi-current))
13100 (moddecls (verilog-modi-get-decls modi))
13101 (modsubdecls (verilog-modi-get-sub-decls modi))
13102 (sig-list (verilog-signals-not-in
13103 (verilog-decls-get-outputs moddecls)
13104 (append (verilog-decls-get-vars moddecls)
13105 (verilog-decls-get-assigns moddecls)
13106 (verilog-decls-get-consts moddecls)
13107 (verilog-decls-get-gparams moddecls)
13108 (verilog-subdecls-get-interfaced modsubdecls)
13109 (verilog-subdecls-get-outputs modsubdecls)
13110 (verilog-subdecls-get-inouts modsubdecls)))))
13111 (setq sig-list (verilog-signals-not-matching-regexp
13112 sig-list verilog-auto-tieoff-ignore-regexp))
13114 (verilog-forward-or-insert-line)
13115 (verilog-insert-indent "// Beginning of automatic tieoffs (for this module's unterminated outputs)\n")
13116 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
13117 (verilog-modi-cache-add-vars modi sig-list) ; Before we trash list
13119 (let ((sig (car sig-list)))
13120 (cond ((equal verilog-auto-tieoff-declaration "assign")
13121 (indent-to indent-pt)
13122 (insert "assign " (verilog-sig-name sig)))
13124 (verilog-insert-one-definition sig verilog-auto-tieoff-declaration indent-pt)))
13125 (indent-to (max 48 (+ indent-pt 40)))
13126 (insert "= " (verilog-sig-tieoff sig)
13128 (setq sig-list (cdr sig-list))))
13129 (verilog-insert-indent "// End of automatics\n")))))
13131 (defun verilog-auto-undef ()
13132 "Expand AUTOUNDEF statements, as part of \\[verilog-auto].
13133 Take any \\=`defines since the last AUTOUNDEF in the current file
13134 and create \\=`undefs for them. This is used to insure that
13135 file-local defines do not pollute the global \\=`define name space.
13138 AUTOUNDEF presumes any identifier following \\=`define is the
13139 name of a define. Any \\=`ifdefs are ignored.
13141 AUTOUNDEF suppresses creating an \\=`undef for any define that was
13142 \\=`undefed before the AUTOUNDEF. This may be used to work around
13143 the ignoring of \\=`ifdefs as shown below.
13148 \\=`define M_BAR(x)
13152 \\=`undef M_BAZ // Emacs will see this and not \\=`undef M_BAZ
13157 Typing \\[verilog-auto] will make this into:
13161 // Beginning of automatic undefs
13164 // End of automatics
13166 You may also provide an optional regular expression, in which case only
13167 defines the regular expression will be undefed."
13169 (let* ((params (verilog-read-auto-params 0 1))
13170 (regexp (nth 0 params))
13171 (indent-pt (current-indentation))
13175 ;; Scan from start of file, or last AUTOUNDEF
13176 (or (verilog-re-search-backward-quick "/\\*AUTOUNDEF\\>" end-pt t)
13177 (goto-char (point-min)))
13178 (while (verilog-re-search-forward-quick
13179 "`\\(define\\|undef\\)\\s-*\\([a-zA-Z_][a-zA-Z_0-9]*\\)" end-pt t)
13180 (cond ((equal (match-string-no-properties 1) "define")
13181 (setq def (match-string-no-properties 2))
13182 (when (and (or (not regexp)
13183 (string-match regexp def))
13184 (not (member def defs))) ; delete-dups not in 21.1
13185 (setq defs (cons def defs))))
13187 (setq defs (delete (match-string-no-properties 2) defs))))))
13189 (setq defs (sort defs 'string<))
13191 (verilog-forward-or-insert-line)
13192 (verilog-insert-indent "// Beginning of automatic undefs\n")
13194 (verilog-insert-indent "`undef " (car defs) "\n")
13195 (setq defs (cdr defs)))
13196 (verilog-insert-indent "// End of automatics\n")))))
13198 (defun verilog-auto-unused ()
13199 "Expand AUTOUNUSED statements, as part of \\[verilog-auto].
13200 Replace the /*AUTOUNUSED*/ comment with a comma separated list of all unused
13201 input and inout signals.
13203 /*AUTOUNUSED*/ is used to make stub modules; modules that have the same
13204 input/output list as another module, but no internals. Specifically, it
13205 finds all inputs and inouts in the module, and if that input is not otherwise
13206 used, adds it to a comma separated list.
13208 The comma separated list is intended to be used to create a _unused_ok
13209 signal. Using the exact name \"_unused_ok\" for name of the temporary
13210 signal is recommended as it will insure maximum forward compatibility, it
13211 also makes lint warnings easy to understand; ignore any unused warnings
13212 with \"unused\" in the signal name.
13214 To reduce simulation time, the _unused_ok signal should be forced to a
13215 constant to prevent wiggling. The easiest thing to do is use a
13216 reduction-and with 1\\='b0 as shown.
13218 This way all unused signals are in one place, making it convenient to add
13219 your tool's specific pragmas around the assignment to disable any unused
13222 You can add signals you do not want included in AUTOUNUSED with
13223 `verilog-auto-unused-ignore-regexp'.
13225 An example of making a stub for another module:
13227 module ExampStub (/*AUTOINST*/);
13228 /*AUTOINOUTPARAM(\"Examp\")*/
13229 /*AUTOINOUTMODULE(\"Examp\")*/
13231 // verilator lint_off UNUSED
13232 wire _unused_ok = &{1\\='b0,
13235 // verilator lint_on UNUSED
13238 Typing \\[verilog-auto] will make this into:
13241 // verilator lint_off UNUSED
13242 wire _unused_ok = &{1\\='b0,
13244 // Beginning of automatics
13248 // End of automatics
13250 // verilator lint_on UNUSED
13255 (let* ((indent-pt (progn (search-backward "/*") (current-column)))
13256 (modi (verilog-modi-current))
13257 (moddecls (verilog-modi-get-decls modi))
13258 (modsubdecls (verilog-modi-get-sub-decls modi))
13259 (sig-list (verilog-signals-not-in
13260 (append (verilog-decls-get-inputs moddecls)
13261 (verilog-decls-get-inouts moddecls))
13262 (append (verilog-subdecls-get-inputs modsubdecls)
13263 (verilog-subdecls-get-inouts modsubdecls)))))
13264 (setq sig-list (verilog-signals-not-matching-regexp
13265 sig-list verilog-auto-unused-ignore-regexp))
13267 (verilog-forward-or-insert-line)
13268 (verilog-insert-indent "// Beginning of automatic unused inputs\n")
13269 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
13271 (let ((sig (car sig-list)))
13272 (indent-to indent-pt)
13273 (insert (verilog-sig-name sig) ",\n")
13274 (setq sig-list (cdr sig-list))))
13275 (verilog-insert-indent "// End of automatics\n")))))
13277 (defun verilog-enum-ascii (signm elim-regexp)
13278 "Convert an enum name SIGNM to an ascii string for insertion.
13279 Remove user provided prefix ELIM-REGEXP."
13280 (or elim-regexp (setq elim-regexp "_ DONT MATCH IT_"))
13281 (let ((case-fold-search t))
13282 ;; All upper becomes all lower for readability
13283 (downcase (verilog-string-replace-matches elim-regexp "" nil nil signm))))
13285 (defun verilog-auto-ascii-enum ()
13286 "Expand AUTOASCIIENUM statements, as part of \\[verilog-auto].
13287 Create a register to contain the ASCII decode of an enumerated signal type.
13288 This will allow trace viewers to show the ASCII name of states.
13290 First, parameters are built into an enumeration using the synopsys enum
13291 comment. The comment must be between the keyword and the symbol.
13292 \(Annoying, but that's what Synopsys's dc_shell FSM reader requires.)
13294 Next, registers which that enum applies to are also tagged with the same
13297 Finally, an AUTOASCIIENUM command is used.
13299 The first parameter is the name of the signal to be decoded.
13301 The second parameter is the name to store the ASCII code into. For the
13302 signal foo, I suggest the name _foo__ascii, where the leading _ indicates
13303 a signal that is just for simulation, and the magic characters _ascii
13304 tell viewers like Dinotrace to display in ASCII format.
13306 The third optional parameter is a string which will be removed
13307 from the state names. It defaults to \"\" which removes nothing.
13309 The fourth optional parameter is \"onehot\" to force one-hot
13310 decoding. If unspecified, if and only if the first parameter
13311 width is 2^(number of states in enum) and does NOT match the
13312 width of the enum, the signal is assumed to be a one-hot
13313 decode. Otherwise, it's a normal encoded state vector.
13315 `verilog-auto-wire-type' may be used to change the datatype of
13318 \"auto enum\" may be used in place of \"synopsys enum\".
13322 //== State enumeration
13323 parameter [2:0] // synopsys enum state_info
13324 SM_IDLE = 3\\='b000,
13325 SM_SEND = 3\\='b001,
13326 SM_WAIT1 = 3\\='b010;
13327 //== State variables
13328 reg [2:0] /* synopsys enum state_info */
13329 state_r; /* synopsys state_vector state_r */
13330 reg [2:0] /* synopsys enum state_info */
13333 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
13335 Typing \\[verilog-auto] will make this into:
13337 ... same front matter ...
13339 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
13340 // Beginning of automatic ASCII enum decoding
13341 reg [39:0] state_ascii_r; // Decode of state_r
13342 always @(state_r) begin
13344 SM_IDLE: state_ascii_r = \"idle \";
13345 SM_SEND: state_ascii_r = \"send \";
13346 SM_WAIT1: state_ascii_r = \"wait1\";
13347 default: state_ascii_r = \"%Erro\";
13350 // End of automatics"
13352 (let* ((params (verilog-read-auto-params 2 4))
13353 (undecode-name (nth 0 params))
13354 (ascii-name (nth 1 params))
13355 (elim-regexp (and (nth 2 params)
13356 (not (equal (nth 2 params) ""))
13358 (one-hot-flag (nth 3 params))
13360 (indent-pt (current-indentation))
13361 (modi (verilog-modi-current))
13362 (moddecls (verilog-modi-get-decls modi))
13364 (sig-list-consts (append (verilog-decls-get-consts moddecls)
13365 (verilog-decls-get-gparams moddecls)))
13366 (sig-list-all (verilog-decls-get-iovars moddecls))
13368 (undecode-sig (or (assoc undecode-name sig-list-all)
13369 (error "%s: Signal `%s' not found in design"
13370 (verilog-point-text) undecode-name)))
13371 (undecode-enum (or (verilog-sig-enum undecode-sig)
13372 (error "%s: Signal `%s' does not have an enum tag"
13373 (verilog-point-text) undecode-name)))
13375 (enum-sigs (verilog-signals-not-in
13376 (or (verilog-signals-matching-enum sig-list-consts undecode-enum)
13377 (error "%s: No state definitions for `%s'"
13378 (verilog-point-text) undecode-enum))
13382 (string-match "onehot" (or one-hot-flag ""))
13383 (and ; width(enum) != width(sig)
13384 (or (not (verilog-sig-bits (car enum-sigs)))
13385 (not (equal (verilog-sig-width (car enum-sigs))
13386 (verilog-sig-width undecode-sig))))
13387 ;; count(enums) == width(sig)
13388 (equal (number-to-string (length enum-sigs))
13389 (verilog-sig-width undecode-sig)))))
13393 ;; Find number of ascii chars needed
13394 (let ((tmp-sigs enum-sigs))
13396 (setq enum-chars (max enum-chars (length (verilog-sig-name (car tmp-sigs))))
13397 ascii-chars (max ascii-chars (length (verilog-enum-ascii
13398 (verilog-sig-name (car tmp-sigs))
13400 tmp-sigs (cdr tmp-sigs))))
13402 (verilog-forward-or-insert-line)
13403 (verilog-insert-indent "// Beginning of automatic ASCII enum decoding\n")
13404 (let ((decode-sig-list (list (list ascii-name (format "[%d:0]" (- (* ascii-chars 8) 1))
13405 (concat "Decode of " undecode-name) nil nil))))
13406 (verilog-insert-definition modi decode-sig-list "reg" indent-pt nil))
13408 (verilog-insert-indent "always @(" undecode-name ") begin\n")
13409 (setq indent-pt (+ indent-pt verilog-indent-level))
13410 (verilog-insert-indent "case ({" undecode-name "})\n")
13411 (setq indent-pt (+ indent-pt verilog-case-indent))
13413 (let ((tmp-sigs enum-sigs)
13414 (chrfmt (format "%%-%ds %s = \"%%-%ds\";\n"
13415 (+ (if one-hot 9 1) (max 8 enum-chars))
13416 ascii-name ascii-chars))
13417 (errname (substring "%Error" 0 (min 6 ascii-chars))))
13419 (verilog-insert-indent
13422 (concat (if one-hot "(")
13423 ;; Use enum-sigs length as that's numeric
13424 ;; verilog-sig-width undecode-sig might not be.
13425 (if one-hot (number-to-string (length enum-sigs)))
13426 ;; We use a shift instead of var[index]
13427 ;; so that a non-one hot value will show as error.
13428 (if one-hot "'b1<<")
13429 (verilog-sig-name (car tmp-sigs))
13430 (if one-hot ")") ":")
13431 (verilog-enum-ascii (verilog-sig-name (car tmp-sigs))
13433 (setq tmp-sigs (cdr tmp-sigs)))
13434 (verilog-insert-indent (format chrfmt "default:" errname)))
13436 (setq indent-pt (- indent-pt verilog-case-indent))
13437 (verilog-insert-indent "endcase\n")
13438 (setq indent-pt (- indent-pt verilog-indent-level))
13439 (verilog-insert-indent "end\n"
13440 "// End of automatics\n"))))
13442 (defun verilog-auto-templated-rel ()
13443 "Replace Templated relative line numbers with absolute line numbers.
13444 Internal use only. This hacks around the line numbers in AUTOINST Templates
13445 being different from the final output's line numbering."
13446 (let ((templateno 0) (template-line (list 0)) (buf-line 1))
13447 ;; Find line number each template is on
13448 ;; Count lines as we go, as otherwise it's O(n^2) to use count-lines
13449 (goto-char (point-min))
13450 (while (not (eobp))
13451 (when (looking-at ".*AUTO_TEMPLATE")
13452 (setq templateno (1+ templateno))
13453 (setq template-line (cons buf-line template-line)))
13454 (setq buf-line (1+ buf-line))
13456 (setq template-line (nreverse template-line))
13457 ;; Replace T# L# with absolute line number
13458 (goto-char (point-min))
13459 (while (re-search-forward " Templated T\\([0-9]+\\) L\\([0-9]+\\)" nil t)
13461 (concat " Templated "
13462 (int-to-string (+ (nth (string-to-number (match-string 1))
13464 (string-to-number (match-string 2)))))
13467 (defun verilog-auto-template-lint ()
13468 "Check AUTO_TEMPLATEs for unused lines.
13469 Enable with `verilog-auto-template-warn-unused'."
13470 (let ((name1 (or (buffer-file-name) (buffer-name))))
13472 (goto-char (point-min))
13473 (while (re-search-forward
13474 "^\\s-*/?\\*?\\s-*[a-zA-Z0-9`_$]+\\s-+AUTO_TEMPLATE" nil t)
13475 (let* ((tpl-info (verilog-read-auto-template-middle))
13476 (tpl-list (aref tpl-info 1))
13477 (tlines (append (nth 0 tpl-list) (nth 1 tpl-list)))
13480 (setq tpl-ass (car tlines)
13481 tlines (cdr tlines))
13483 (unless (or (not (eval-when-compile (fboundp 'make-hash-table))) ; Not supported, no warning
13484 (not verilog-auto-template-hits)
13485 (gethash (vector (nth 2 tpl-ass) (nth 3 tpl-ass))
13486 verilog-auto-template-hits))
13487 (verilog-warn-error "%s:%d: AUTO_TEMPLATE line unused: \".%s (%s)\""
13489 (+ (elt tpl-ass 3) ; Template line number
13490 (count-lines (point-min) (point)))
13491 (elt tpl-ass 0) (elt tpl-ass 1))
13495 ;;; Auto top level:
13498 (defun verilog-auto (&optional inject) ; Use verilog-inject-auto instead of passing an arg
13499 "Expand AUTO statements.
13500 Look for any /*AUTO...*/ commands in the code, as used in
13501 instantiations or argument headers. Update the list of signals
13502 following the /*AUTO...*/ command.
13504 Use \\[verilog-delete-auto] to remove the AUTOs.
13506 Use \\[verilog-diff-auto] to see differences in AUTO expansion.
13508 Use \\[verilog-inject-auto] to insert AUTOs for the first time.
13510 Use \\[verilog-faq] for a pointer to frequently asked questions.
13512 For new users, we recommend setting `verilog-case-fold' to nil
13513 and `verilog-auto-arg-sort' to t.
13515 The hooks `verilog-before-auto-hook' and `verilog-auto-hook' are
13516 called before and after this function, respectively.
13519 module ModuleName (/*AUTOARG*/);
13524 InstMod instName #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);
13526 You can also update the AUTOs from the shell using:
13527 emacs --batch <filenames.v> -f verilog-batch-auto
13528 Or fix indentation with:
13529 emacs --batch <filenames.v> -f verilog-batch-indent
13530 Likewise, you can delete or inject AUTOs with:
13531 emacs --batch <filenames.v> -f verilog-batch-delete-auto
13532 emacs --batch <filenames.v> -f verilog-batch-inject-auto
13533 Or check if AUTOs have the same expansion
13534 emacs --batch <filenames.v> -f verilog-batch-diff-auto
13536 Using \\[describe-function], see also:
13537 `verilog-auto-arg' for AUTOARG module instantiations
13538 `verilog-auto-ascii-enum' for AUTOASCIIENUM enumeration decoding
13539 `verilog-auto-assign-modport' for AUTOASSIGNMODPORT assignment to/from modport
13540 `verilog-auto-inout' for AUTOINOUT making hierarchy inouts
13541 `verilog-auto-inout-comp' for AUTOINOUTCOMP copy complemented i/o
13542 `verilog-auto-inout-in' for AUTOINOUTIN inputs for all i/o
13543 `verilog-auto-inout-modport' for AUTOINOUTMODPORT i/o from an interface modport
13544 `verilog-auto-inout-module' for AUTOINOUTMODULE copying i/o from elsewhere
13545 `verilog-auto-inout-param' for AUTOINOUTPARAM copying params from elsewhere
13546 `verilog-auto-input' for AUTOINPUT making hierarchy inputs
13547 `verilog-auto-insert-lisp' for AUTOINSERTLISP insert code from lisp function
13548 `verilog-auto-insert-last' for AUTOINSERTLAST insert code from lisp function
13549 `verilog-auto-inst' for AUTOINST instantiation pins
13550 `verilog-auto-star' for AUTOINST .* SystemVerilog pins
13551 `verilog-auto-inst-param' for AUTOINSTPARAM instantiation params
13552 `verilog-auto-logic' for AUTOLOGIC declaring logic signals
13553 `verilog-auto-output' for AUTOOUTPUT making hierarchy outputs
13554 `verilog-auto-output-every' for AUTOOUTPUTEVERY making all outputs
13555 `verilog-auto-reg' for AUTOREG registers
13556 `verilog-auto-reg-input' for AUTOREGINPUT instantiation registers
13557 `verilog-auto-reset' for AUTORESET flop resets
13558 `verilog-auto-sense' for AUTOSENSE or AS always sensitivity lists
13559 `verilog-auto-tieoff' for AUTOTIEOFF output tieoffs
13560 `verilog-auto-undef' for AUTOUNDEF \\=`undef of local \\=`defines
13561 `verilog-auto-unused' for AUTOUNUSED unused inputs/inouts
13562 `verilog-auto-wire' for AUTOWIRE instantiation wires
13564 `verilog-read-defines' for reading \\=`define values
13565 `verilog-read-includes' for reading \\=`includes
13567 If you have bugs with these autos, please file an issue at
13568 URL `http://www.veripool.org/verilog-mode' or contact the AUTOAUTHOR
13569 Wilson Snyder (wsnyder@wsnyder.org)."
13571 (unless noninteractive (message "Updating AUTOs..."))
13572 (if (fboundp 'dinotrace-unannotate-all)
13573 (dinotrace-unannotate-all))
13574 ;; Disable change hooks for speed
13575 ;; This let can't be part of above let; must restore
13576 ;; after-change-functions before font-lock resumes
13577 (verilog-save-font-no-change-functions
13578 (let ((oldbuf (if (not (buffer-modified-p))
13580 (case-fold-search verilog-case-fold)
13581 ;; Cache directories; we don't write new files, so can't change
13582 (verilog-dir-cache-preserving t)
13583 ;; Cache current module
13584 (verilog-modi-cache-current-enable t)
13585 (verilog-modi-cache-current-max (point-min)) ; IE it's invalid
13586 verilog-modi-cache-current)
13587 (verilog-save-scan-cache
13589 ;; Wipe cache; otherwise if we AUTOed a block above this one,
13590 ;; we'll misremember we have generated IOs, confusing AUTOOUTPUT
13591 (setq verilog-modi-cache-list nil)
13593 (verilog-read-auto-template-init)
13594 ;; If we're not in verilog-mode, change syntax table so parsing works right
13595 (unless (eq major-mode `verilog-mode) (verilog-mode))
13596 ;; Allow user to customize
13597 (verilog-run-hooks 'verilog-before-auto-hook)
13598 ;; Try to save the user from needing to revert-file to reread file local-variables
13599 (verilog-auto-reeval-locals)
13600 (verilog-read-auto-lisp-present)
13601 (verilog-read-auto-lisp (point-min) (point-max))
13602 (verilog-getopt-flags)
13603 ;; From here on out, we can cache anything we read from disk
13604 (verilog-preserve-dir-cache
13605 ;; These two may seem obvious to do always, but on large includes it can be way too slow
13606 (when verilog-auto-read-includes
13607 (verilog-read-includes)
13608 (verilog-read-defines nil nil t))
13609 ;; Setup variables due to SystemVerilog expansion
13610 (verilog-auto-re-search-do "/\\*AUTOLOGIC\\*/" 'verilog-auto-logic-setup)
13611 ;; This particular ordering is important
13612 ;; INST: Lower modules correct, no internal dependencies, FIRST
13613 (verilog-preserve-modi-cache
13614 ;; Clear existing autos else we'll be screwed by existing ones
13615 (verilog-delete-auto-buffer)
13616 ;; Injection if appropriate
13618 (verilog-inject-inst)
13619 (verilog-inject-sense)
13620 (verilog-inject-arg))
13622 ;; Do user inserts first, so their code can insert AUTOs
13623 (verilog-auto-re-search-do "/\\*AUTOINSERTLISP(.*?)\\*/"
13624 'verilog-auto-insert-lisp)
13625 ;; Expand instances before need the signals the instances input/output
13626 (verilog-auto-re-search-do "/\\*AUTOINSTPARAM\\*/" 'verilog-auto-inst-param)
13627 (verilog-auto-re-search-do "/\\*AUTOINST\\*/" 'verilog-auto-inst)
13628 (verilog-auto-re-search-do "\\.\\*" 'verilog-auto-star)
13629 ;; Doesn't matter when done, but combine it with a common changer
13630 (verilog-auto-re-search-do "/\\*\\(AUTOSENSE\\|AS\\)\\*/" 'verilog-auto-sense)
13631 (verilog-auto-re-search-do "/\\*AUTORESET\\*/" 'verilog-auto-reset)
13632 ;; Must be done before autoin/out as creates a reg
13633 (verilog-auto-re-search-do "/\\*AUTOASCIIENUM(.*?)\\*/" 'verilog-auto-ascii-enum)
13635 ;; first in/outs from other files
13636 (verilog-auto-re-search-do "/\\*AUTOINOUTMODPORT(.*?)\\*/" 'verilog-auto-inout-modport)
13637 (verilog-auto-re-search-do "/\\*AUTOINOUTMODULE(.*?)\\*/" 'verilog-auto-inout-module)
13638 (verilog-auto-re-search-do "/\\*AUTOINOUTCOMP(.*?)\\*/" 'verilog-auto-inout-comp)
13639 (verilog-auto-re-search-do "/\\*AUTOINOUTIN(.*?)\\*/" 'verilog-auto-inout-in)
13640 (verilog-auto-re-search-do "/\\*AUTOINOUTPARAM(.*?)\\*/" 'verilog-auto-inout-param)
13641 ;; next in/outs which need previous sucked inputs first
13642 (verilog-auto-re-search-do "/\\*AUTOOUTPUT\\((.*?)\\)?\\*/" 'verilog-auto-output)
13643 (verilog-auto-re-search-do "/\\*AUTOINPUT\\((.*?)\\)?\\*/" 'verilog-auto-input)
13644 (verilog-auto-re-search-do "/\\*AUTOINOUT\\((.*?)\\)?\\*/" 'verilog-auto-inout)
13645 ;; Then tie off those in/outs
13646 (verilog-auto-re-search-do "/\\*AUTOTIEOFF\\*/" 'verilog-auto-tieoff)
13647 ;; These can be anywhere after AUTOINSERTLISP
13648 (verilog-auto-re-search-do "/\\*AUTOUNDEF\\((.*?)\\)?\\*/" 'verilog-auto-undef)
13649 ;; Wires/regs must be after inputs/outputs
13650 (verilog-auto-re-search-do "/\\*AUTOASSIGNMODPORT(.*?)\\*/" 'verilog-auto-assign-modport)
13651 (verilog-auto-re-search-do "/\\*AUTOLOGIC\\*/" 'verilog-auto-logic)
13652 (verilog-auto-re-search-do "/\\*AUTOWIRE\\*/" 'verilog-auto-wire)
13653 (verilog-auto-re-search-do "/\\*AUTOREG\\*/" 'verilog-auto-reg)
13654 (verilog-auto-re-search-do "/\\*AUTOREGINPUT\\*/" 'verilog-auto-reg-input)
13655 ;; outputevery needs AUTOOUTPUTs done first
13656 (verilog-auto-re-search-do "/\\*AUTOOUTPUTEVERY\\((.*?)\\)?\\*/" 'verilog-auto-output-every)
13657 ;; After we've created all new variables
13658 (verilog-auto-re-search-do "/\\*AUTOUNUSED\\*/" 'verilog-auto-unused)
13659 ;; Must be after all inputs outputs are generated
13660 (verilog-auto-re-search-do "/\\*AUTOARG\\*/" 'verilog-auto-arg)
13662 (verilog-auto-re-search-do "/\\*AUTOINSERTLAST(.*?)\\*/" 'verilog-auto-insert-last)
13663 ;; Fix line numbers (comments only)
13664 (when verilog-auto-inst-template-numbers
13665 (verilog-auto-templated-rel))
13666 (when verilog-auto-template-warn-unused
13667 (verilog-auto-template-lint))))
13669 (verilog-run-hooks 'verilog-auto-hook)
13671 (when verilog-auto-delete-trailing-whitespace
13672 (verilog-delete-trailing-whitespace))
13674 (set (make-local-variable 'verilog-auto-update-tick) (buffer-chars-modified-tick))
13676 ;; If end result is same as when started, clear modified flag
13677 (cond ((and oldbuf (equal oldbuf (buffer-string)))
13678 (verilog-restore-buffer-modified-p nil)
13679 (unless noninteractive (message "Updating AUTOs...done (no changes)")))
13680 (t (unless noninteractive (message "Updating AUTOs...done"))))
13681 ;; End of save-cache
13687 (defvar verilog-template-map
13688 (let ((map (make-sparse-keymap)))
13689 (define-key map "a" 'verilog-sk-always)
13690 (define-key map "b" 'verilog-sk-begin)
13691 (define-key map "c" 'verilog-sk-case)
13692 (define-key map "f" 'verilog-sk-for)
13693 (define-key map "g" 'verilog-sk-generate)
13694 (define-key map "h" 'verilog-sk-header)
13695 (define-key map "i" 'verilog-sk-initial)
13696 (define-key map "j" 'verilog-sk-fork)
13697 (define-key map "m" 'verilog-sk-module)
13698 (define-key map "o" 'verilog-sk-ovm-class)
13699 (define-key map "p" 'verilog-sk-primitive)
13700 (define-key map "r" 'verilog-sk-repeat)
13701 (define-key map "s" 'verilog-sk-specify)
13702 (define-key map "t" 'verilog-sk-task)
13703 (define-key map "u" 'verilog-sk-uvm-object)
13704 (define-key map "w" 'verilog-sk-while)
13705 (define-key map "x" 'verilog-sk-casex)
13706 (define-key map "z" 'verilog-sk-casez)
13707 (define-key map "?" 'verilog-sk-if)
13708 (define-key map ":" 'verilog-sk-else-if)
13709 (define-key map "/" 'verilog-sk-comment)
13710 (define-key map "A" 'verilog-sk-assign)
13711 (define-key map "F" 'verilog-sk-function)
13712 (define-key map "I" 'verilog-sk-input)
13713 (define-key map "O" 'verilog-sk-output)
13714 (define-key map "S" 'verilog-sk-state-machine)
13715 (define-key map "=" 'verilog-sk-inout)
13716 (define-key map "U" 'verilog-sk-uvm-component)
13717 (define-key map "W" 'verilog-sk-wire)
13718 (define-key map "R" 'verilog-sk-reg)
13719 (define-key map "D" 'verilog-sk-define-signal)
13721 "Keymap used in Verilog mode for smart template operations.")
13725 ;; Place the templates into Verilog Mode. They may be inserted under any key.
13726 ;; C-c C-t will be the default. If you use templates a lot, you
13727 ;; may want to consider moving the binding to another key in your init
13730 ;; Note \C-c and letter are reserved for users
13731 (define-key verilog-mode-map "\C-c\C-t" verilog-template-map)
13733 ;; ---- statement skeletons ------------------------------------------
13735 (define-skeleton verilog-sk-prompt-condition
13736 "Prompt for the loop condition."
13737 "[condition]: " str )
13739 (define-skeleton verilog-sk-prompt-init
13740 "Prompt for the loop init statement."
13741 "[initial statement]: " str )
13743 (define-skeleton verilog-sk-prompt-inc
13744 "Prompt for the loop increment statement."
13745 "[increment statement]: " str )
13747 (define-skeleton verilog-sk-prompt-name
13748 "Prompt for the name of something."
13751 (define-skeleton verilog-sk-prompt-clock
13752 "Prompt for the name of something."
13753 "name and edge of clock(s): " str)
13755 (defvar verilog-sk-reset nil)
13756 (defun verilog-sk-prompt-reset ()
13757 "Prompt for the name of a state machine reset."
13758 (setq verilog-sk-reset (read-string "name of reset: " "rst")))
13761 (define-skeleton verilog-sk-prompt-state-selector
13762 "Prompt for the name of a state machine selector."
13763 "name of selector (eg {a,b,c,d}): " str )
13765 (define-skeleton verilog-sk-prompt-output
13766 "Prompt for the name of something."
13769 (define-skeleton verilog-sk-prompt-msb
13770 "Prompt for most significant bit specification."
13771 "msb:" str & ?: & '(verilog-sk-prompt-lsb) | -1 )
13773 (define-skeleton verilog-sk-prompt-lsb
13774 "Prompt for least significant bit specification."
13777 (defvar verilog-sk-p nil)
13778 (define-skeleton verilog-sk-prompt-width
13779 "Prompt for a width specification."
13782 (setq verilog-sk-p (point))
13783 (verilog-sk-prompt-msb)
13784 (if (> (point) verilog-sk-p) "] " " ")))
13786 (defun verilog-sk-header ()
13787 "Insert a descriptive header at the top of the file.
13788 See also `verilog-header' for an alternative format."
13791 (goto-char (point-min))
13792 (verilog-sk-header-tmpl)))
13794 (define-skeleton verilog-sk-header-tmpl
13795 "Insert a comment block containing the module title, author, etc."
13797 "// -*- Mode: Verilog -*-"
13798 "\n// Filename : " (buffer-name)
13799 "\n// Description : " str
13800 "\n// Author : " (user-full-name)
13801 "\n// Created On : " (current-time-string)
13802 "\n// Last Modified By: " (user-full-name)
13803 "\n// Last Modified On: " (current-time-string)
13804 "\n// Update Count : 0"
13805 "\n// Status : Unknown, Use with caution!"
13808 (define-skeleton verilog-sk-module
13809 "Insert a module definition."
13811 > "module " '(verilog-sk-prompt-name) " (/*AUTOARG*/ ) ;" \n
13813 > (- verilog-indent-level-behavioral) "endmodule" (progn (electric-verilog-terminate-line) nil))
13815 ;; ------------------------------------------------------------------------
13816 ;; Define a default OVM class, with macros and new()
13817 ;; ------------------------------------------------------------------------
13819 (define-skeleton verilog-sk-ovm-class
13820 "Insert a class definition"
13822 > "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n
13824 > "`ovm_object_utils_begin(" name ")" \n
13825 > (- verilog-indent-level) " `ovm_object_utils_end" \n
13827 > "function new(string name=\"" name "\");" \n
13828 > "super.new(name);" \n
13829 > (- verilog-indent-level) "endfunction" \n
13831 > "endclass" (progn (electric-verilog-terminate-line) nil))
13833 (define-skeleton verilog-sk-uvm-object
13834 "Insert a class definition"
13836 > "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n
13838 > "`uvm_object_utils_begin(" name ")" \n
13839 > (- verilog-indent-level) "`uvm_object_utils_end" \n
13841 > "function new(string name=\"" name "\");" \n
13842 > "super.new(name);" \n
13843 > (- verilog-indent-level) "endfunction" \n
13845 > "endclass" (progn (electric-verilog-terminate-line) nil))
13847 (define-skeleton verilog-sk-uvm-component
13848 "Insert a class definition"
13850 > "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n
13852 > "`uvm_component_utils_begin(" name ")" \n
13853 > (- verilog-indent-level) "`uvm_component_utils_end" \n
13855 > "function new(string name=\"\", uvm_component parent);" \n
13856 > "super.new(name, parent);" \n
13857 > (- verilog-indent-level) "endfunction" \n
13859 > "endclass" (progn (electric-verilog-terminate-line) nil))
13861 (define-skeleton verilog-sk-primitive
13862 "Insert a task definition."
13864 > "primitive " '(verilog-sk-prompt-name) " ( " '(verilog-sk-prompt-output) ("input:" ", " str ) " );"\n
13866 > (- verilog-indent-level-behavioral) "endprimitive" (progn (electric-verilog-terminate-line) nil))
13868 (define-skeleton verilog-sk-task
13869 "Insert a task definition."
13871 > "task " '(verilog-sk-prompt-name) & ?; \n
13875 > (- verilog-indent-level-behavioral) "end" \n
13876 > (- verilog-indent-level-behavioral) "endtask" (progn (electric-verilog-terminate-line) nil))
13878 (define-skeleton verilog-sk-function
13879 "Insert a function definition."
13881 > "function [" '(verilog-sk-prompt-width) | -1 '(verilog-sk-prompt-name) ?; \n
13885 > (- verilog-indent-level-behavioral) "end" \n
13886 > (- verilog-indent-level-behavioral) "endfunction" (progn (electric-verilog-terminate-line) nil))
13888 (define-skeleton verilog-sk-always
13889 "Insert always block. Uses the minibuffer to prompt
13890 for sensitivity list."
13892 > "always @ ( /*AUTOSENSE*/ ) begin\n"
13894 > (- verilog-indent-level-behavioral) "end" \n >
13897 (define-skeleton verilog-sk-initial
13898 "Insert an initial block."
13900 > "initial begin\n"
13902 > (- verilog-indent-level-behavioral) "end" \n > )
13904 (define-skeleton verilog-sk-specify
13905 "Insert specify block. "
13909 > (- verilog-indent-level-behavioral) "endspecify" \n > )
13911 (define-skeleton verilog-sk-generate
13912 "Insert generate block. "
13916 > (- verilog-indent-level-behavioral) "endgenerate" \n > )
13918 (define-skeleton verilog-sk-begin
13919 "Insert begin end block. Uses the minibuffer to prompt for name."
13921 > "begin" '(verilog-sk-prompt-name) \n
13923 > (- verilog-indent-level-behavioral) "end" )
13925 (define-skeleton verilog-sk-fork
13926 "Insert a fork join block."
13931 > (- verilog-indent-level-behavioral) "end" \n
13934 > (- verilog-indent-level-behavioral) "end" \n
13935 > (- verilog-indent-level-behavioral) "join" \n
13939 (define-skeleton verilog-sk-case
13940 "Build skeleton case statement, prompting for the selector expression,
13941 and the case items."
13942 "[selector expression]: "
13943 > "case (" str ") " \n
13944 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
13945 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
13947 (define-skeleton verilog-sk-casex
13948 "Build skeleton casex statement, prompting for the selector expression,
13949 and the case items."
13950 "[selector expression]: "
13951 > "casex (" str ") " \n
13952 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
13953 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
13955 (define-skeleton verilog-sk-casez
13956 "Build skeleton casez statement, prompting for the selector expression,
13957 and the case items."
13958 "[selector expression]: "
13959 > "casez (" str ") " \n
13960 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
13961 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
13963 (define-skeleton verilog-sk-if
13964 "Insert a skeleton if statement."
13965 > "if (" '(verilog-sk-prompt-condition) & ")" " begin" \n
13967 > (- verilog-indent-level-behavioral) "end " \n )
13969 (define-skeleton verilog-sk-else-if
13970 "Insert a skeleton else if statement."
13971 > (verilog-indent-line) "else if ("
13972 (progn (setq verilog-sk-p (point)) nil) '(verilog-sk-prompt-condition) (if (> (point) verilog-sk-p) ") " -1 ) & " begin" \n
13974 > "end" (progn (electric-verilog-terminate-line) nil))
13976 (define-skeleton verilog-sk-datadef
13977 "Common routine to get data definition."
13979 '(verilog-sk-prompt-width) | -1 ("name (RET to end):" str ", ") -2 ";" \n)
13981 (define-skeleton verilog-sk-input
13982 "Insert an input definition."
13984 > "input [" '(verilog-sk-datadef))
13986 (define-skeleton verilog-sk-output
13987 "Insert an output definition."
13989 > "output [" '(verilog-sk-datadef))
13991 (define-skeleton verilog-sk-inout
13992 "Insert an inout definition."
13994 > "inout [" '(verilog-sk-datadef))
13996 (defvar verilog-sk-signal nil)
13997 (define-skeleton verilog-sk-def-reg
13998 "Insert a reg definition."
14000 > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-signal ";" \n (verilog-pretty-declarations-auto) )
14002 (defun verilog-sk-define-signal ()
14003 "Insert a definition of signal under point at top of module."
14005 (let* ((sig-re "[a-zA-Z0-9_]*")
14006 (v1 (buffer-substring
14008 (skip-chars-backward sig-re)
14011 (skip-chars-forward sig-re)
14013 (if (not (member v1 verilog-keywords))
14015 (setq verilog-sk-signal v1)
14016 (verilog-beg-of-defun)
14017 (verilog-end-of-statement)
14018 (verilog-forward-syntactic-ws)
14019 (verilog-sk-def-reg)
14020 (message "signal at point is %s" v1))
14021 (message "object at point (%s) is a keyword" v1))))
14023 (define-skeleton verilog-sk-wire
14024 "Insert a wire definition."
14026 > "wire [" '(verilog-sk-datadef))
14028 (define-skeleton verilog-sk-reg
14029 "Insert a reg definition."
14031 > "reg [" '(verilog-sk-datadef))
14033 (define-skeleton verilog-sk-assign
14034 "Insert a skeleton assign statement."
14036 > "assign " '(verilog-sk-prompt-name) " = " _ ";" \n)
14038 (define-skeleton verilog-sk-while
14039 "Insert a skeleton while loop statement."
14041 > "while (" '(verilog-sk-prompt-condition) ") begin" \n
14043 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
14045 (define-skeleton verilog-sk-repeat
14046 "Insert a skeleton repeat loop statement."
14048 > "repeat (" '(verilog-sk-prompt-condition) ") begin" \n
14050 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
14052 (define-skeleton verilog-sk-for
14053 "Insert a skeleton while loop statement."
14056 '(verilog-sk-prompt-init) "; "
14057 '(verilog-sk-prompt-condition) "; "
14058 '(verilog-sk-prompt-inc)
14061 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
14063 (define-skeleton verilog-sk-comment
14064 "Inserts three comment lines, making a display comment."
14070 (define-skeleton verilog-sk-state-machine
14071 "Insert a state machine definition."
14072 "Name of state variable: "
14073 '(setq input "state")
14074 > "// State registers for " str | -23 \n
14075 '(setq verilog-sk-state str)
14076 > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-state ", next_" verilog-sk-state ?; \n
14079 > "// State FF for " verilog-sk-state \n
14080 > "always @ ( " (read-string "clock:" "posedge clk") " or " (verilog-sk-prompt-reset) " ) begin" \n
14081 > "if ( " verilog-sk-reset " ) " verilog-sk-state " = 0; else" \n
14082 > verilog-sk-state " = next_" verilog-sk-state ?; \n
14083 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil)
14085 > "// Next State Logic for " verilog-sk-state \n
14086 > "always @ ( /*AUTOSENSE*/ ) begin\n"
14087 > "case (" '(verilog-sk-prompt-state-selector) ") " \n
14088 > ("case selector: " str ": begin" \n > "next_" verilog-sk-state " = " _ ";" \n > (- verilog-indent-level-behavioral) "end" \n )
14089 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil)
14090 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil))
14094 ;; Include file loading with mouse/return event
14096 ;; idea & first impl.: M. Rouat (eldo-mode.el)
14097 ;; second (emacs/xemacs) impl.: G. Van der Plas (spice-mode.el)
14099 (if (featurep 'xemacs)
14100 (require 'overlay))
14102 (defconst verilog-include-file-regexp
14103 "^`include\\s-+\"\\([^\n\"]*\\)\""
14104 "Regexp that matches the include file.")
14106 (defvar verilog-mode-mouse-map
14107 (let ((map (make-sparse-keymap))) ; as described in info pages, make a map
14108 (set-keymap-parent map verilog-mode-map)
14109 ;; mouse button bindings
14110 (define-key map "\r" 'verilog-load-file-at-point)
14111 (if (featurep 'xemacs)
14112 (define-key map 'button2 'verilog-load-file-at-mouse);ffap-at-mouse ?
14113 (define-key map [mouse-2] 'verilog-load-file-at-mouse))
14114 (if (featurep 'xemacs)
14115 (define-key map 'Sh-button2 'mouse-yank) ; you wanna paste don't you ?
14116 (define-key map [S-mouse-2] 'mouse-yank-at-click))
14118 "Map containing mouse bindings for `verilog-mode'.")
14121 (defun verilog-highlight-region (beg end _old-len)
14122 "Colorize included files and modules in the (changed?) region.
14123 Clicking on the middle-mouse button loads them in a buffer (as in dired)."
14124 (when (or verilog-highlight-includes
14125 verilog-highlight-modules)
14127 (save-match-data ; A query-replace may call this function - do not disturb
14128 (verilog-save-buffer-state
14129 (verilog-save-scan-cache
14132 (setq end-point (point-at-eol))
14134 (beginning-of-line) ; scan entire line
14135 ;; delete overlays existing on this line
14136 (let ((overlays (overlays-in (point) end-point)))
14139 (overlay-get (car overlays) 'detachable)
14140 (or (overlay-get (car overlays) 'verilog-include-file)
14141 (overlay-get (car overlays) 'verilog-inst-module)))
14142 (delete-overlay (car overlays)))
14143 (setq overlays (cdr overlays))))
14145 ;; make new include overlays
14146 (when verilog-highlight-includes
14147 (while (search-forward-regexp verilog-include-file-regexp end-point t)
14148 (goto-char (match-beginning 1))
14149 (let ((ov (make-overlay (match-beginning 1) (match-end 1))))
14150 (overlay-put ov 'start-closed 't)
14151 (overlay-put ov 'end-closed 't)
14152 (overlay-put ov 'evaporate 't)
14153 (overlay-put ov 'verilog-include-file 't)
14154 (overlay-put ov 'mouse-face 'highlight)
14155 (overlay-put ov 'local-map verilog-mode-mouse-map))))
14157 ;; make new module overlays
14159 ;; This scanner is syntax-fragile, so don't get bent
14160 (when verilog-highlight-modules
14161 (condition-case nil
14162 (while (verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-point t)
14164 (goto-char (match-beginning 0))
14165 (unless (verilog-inside-comment-or-string-p)
14166 (verilog-read-inst-module-matcher) ; sets match 0
14167 (let* ((ov (make-overlay (match-beginning 0) (match-end 0))))
14168 (overlay-put ov 'start-closed 't)
14169 (overlay-put ov 'end-closed 't)
14170 (overlay-put ov 'evaporate 't)
14171 (overlay-put ov 'verilog-inst-module 't)
14172 (overlay-put ov 'mouse-face 'highlight)
14173 (overlay-put ov 'local-map verilog-mode-mouse-map)))))
14176 ;; Future highlights:
14177 ;; variables - make an Occur buffer of where referenced
14178 ;; pins - make an Occur buffer of the sig in the declaration module
14181 (defun verilog-highlight-buffer ()
14182 "Colorize included files and modules across the whole buffer."
14183 ;; Invoked via verilog-mode calling font-lock then `font-lock-mode-hook'
14185 ;; delete and remake overlays
14186 (verilog-highlight-region (point-min) (point-max) nil))
14188 ;; Deprecated, but was interactive, so we'll keep it around
14189 (defalias 'verilog-colorize-include-files-buffer 'verilog-highlight-buffer)
14191 ;; ffap-at-mouse isn't useful for Verilog mode. It uses library paths.
14192 ;; so define this function to do more or less the same as ffap-at-mouse
14193 ;; but first resolve filename...
14194 (defun verilog-load-file-at-mouse (event)
14195 "Load file under button 2 click's EVENT.
14196 Files are checked based on `verilog-library-flags'."
14198 (save-excursion ; implement a Verilog specific ffap-at-mouse
14199 (mouse-set-point event)
14200 (verilog-load-file-at-point t)))
14202 ;; ffap isn't usable for Verilog mode. It uses library paths.
14203 ;; so define this function to do more or less the same as ffap
14204 ;; but first resolve filename...
14205 (defun verilog-load-file-at-point (&optional warn)
14206 "Load file under point.
14207 If WARN, throw warning if not found.
14208 Files are checked based on `verilog-library-flags'."
14210 (save-excursion ; implement a Verilog specific ffap
14211 (let ((overlays (overlays-in (point) (point)))
14213 (while (and overlays (not hit))
14214 (when (overlay-get (car overlays) 'verilog-inst-module)
14215 (verilog-goto-defun-file (buffer-substring
14216 (overlay-start (car overlays))
14217 (overlay-end (car overlays))))
14219 (setq overlays (cdr overlays)))
14221 (beginning-of-line)
14222 (when (and (not hit)
14223 (looking-at verilog-include-file-regexp))
14224 (if (and (car (verilog-library-filenames
14225 (match-string 1) (buffer-file-name)))
14226 (file-readable-p (car (verilog-library-filenames
14227 (match-string 1) (buffer-file-name)))))
14228 (find-file (car (verilog-library-filenames
14229 (match-string 1) (buffer-file-name))))
14232 "File `%s' isn't readable, use shift-mouse2 to paste in this field"
14233 (match-string 1))))))))
14239 (defun verilog-faq ()
14240 "Tell the user their current version, and where to get the FAQ etc."
14242 (with-output-to-temp-buffer "*verilog-mode help*"
14243 (princ (format "You are using verilog-mode %s\n" verilog-mode-version))
14245 (princ "For new releases, see http://www.verilog.com\n")
14247 (princ "For frequently asked questions, see http://www.veripool.org/verilog-mode-faq.html\n")
14249 (princ "To submit a bug, use M-x verilog-submit-bug-report\n")
14252 (autoload 'reporter-submit-bug-report "reporter")
14253 (defvar reporter-prompt-for-summary-p)
14255 (defun verilog-submit-bug-report ()
14256 "Submit via mail a bug report on verilog-mode.el."
14258 (let ((reporter-prompt-for-summary-p t))
14259 (reporter-submit-bug-report
14260 "mac@verilog.com, wsnyder@wsnyder.org"
14261 (concat "verilog-mode v" verilog-mode-version)
14263 verilog-active-low-regexp
14264 verilog-after-save-font-hook
14265 verilog-align-ifelse
14266 verilog-assignment-delay
14267 verilog-auto-arg-sort
14268 verilog-auto-declare-nettype
14269 verilog-auto-delete-trailing-whitespace
14270 verilog-auto-endcomments
14272 verilog-auto-ignore-concat
14273 verilog-auto-indent-on-newline
14274 verilog-auto-inout-ignore-regexp
14275 verilog-auto-input-ignore-regexp
14276 verilog-auto-inst-column
14277 verilog-auto-inst-dot-name
14278 verilog-auto-inst-interfaced-ports
14279 verilog-auto-inst-param-value
14280 verilog-auto-inst-sort
14281 verilog-auto-inst-template-numbers
14282 verilog-auto-inst-vector
14283 verilog-auto-lineup
14284 verilog-auto-newline
14285 verilog-auto-output-ignore-regexp
14286 verilog-auto-read-includes
14287 verilog-auto-reset-blocking-in-non
14288 verilog-auto-reset-widths
14289 verilog-auto-save-policy
14290 verilog-auto-sense-defines-constant
14291 verilog-auto-sense-include-inputs
14292 verilog-auto-star-expand
14293 verilog-auto-star-save
14294 verilog-auto-template-warn-unused
14295 verilog-auto-tieoff-declaration
14296 verilog-auto-tieoff-ignore-regexp
14297 verilog-auto-unused-ignore-regexp
14298 verilog-auto-wire-type
14299 verilog-before-auto-hook
14300 verilog-before-delete-auto-hook
14301 verilog-before-getopt-flags-hook
14302 verilog-before-save-font-hook
14303 verilog-cache-enabled
14305 verilog-case-indent
14306 verilog-cexp-indent
14309 verilog-delete-auto-hook
14310 verilog-getopt-flags-hook
14311 verilog-highlight-grouping-keywords
14312 verilog-highlight-includes
14313 verilog-highlight-modules
14314 verilog-highlight-p1800-keywords
14315 verilog-highlight-translate-off
14316 verilog-indent-begin-after-if
14317 verilog-indent-declaration-macros
14318 verilog-indent-level
14319 verilog-indent-level-behavioral
14320 verilog-indent-level-declaration
14321 verilog-indent-level-directive
14322 verilog-indent-level-module
14323 verilog-indent-lists
14324 verilog-library-directories
14325 verilog-library-extensions
14326 verilog-library-files
14327 verilog-library-flags
14329 verilog-minimum-comment-distance
14331 verilog-mode-release-emacs
14332 verilog-mode-version
14333 verilog-preprocessor
14335 verilog-tab-always-indent
14336 verilog-tab-to-comment
14337 verilog-typedef-regexp
14343 I want to report a bug.
14345 Before I go further, I want to say that Verilog mode has changed my life.
14346 I save so much time, my files are colored nicely, my co workers respect
14347 my coding ability... until now. I'd really appreciate anything you
14348 could do to help me out with this minor deficiency in the product.
14350 I've taken a look at the Verilog-Mode FAQ at
14351 http://www.veripool.org/verilog-mode-faq.html.
14353 And, I've considered filing the bug on the issue tracker at
14354 http://www.veripool.org/verilog-mode-bugs
14355 since I realize that public bugs are easier for you to track,
14356 and for others to search, but would prefer to email.
14358 So, to reproduce the bug, start a fresh Emacs via " invocation-name "
14359 -no-init-file -no-site-file'. In a new buffer, in Verilog mode, type
14360 the code included below.
14362 Given those lines, I expected [[Fill in here]] to happen;
14363 but instead, [[Fill in here]] happens!.
14365 == The code: =="))))
14367 (provide 'verilog-mode)
14369 ;; Local Variables:
14370 ;; checkdoc-permit-comma-termination-flag:t
14371 ;; checkdoc-force-docstrings-flag:nil
14372 ;; indent-tabs-mode:nil
14375 ;;; verilog-mode.el ends here